# AN ASIC IMPLEMENTATION OF THE TWO-DIMENSIONAL DISCRETE COSINE TRANSFORM-thesis, vlsi

Image data compression has been an active research area for image processing over the last decade and has been used in a variety of applications. This thesis investigates the implementation of an image data compression method with VLSI hardware that could be used in practical coding systems to compress real-time video signals. In practical situations, an image is originally defined over a large matrix of picture elements (pixels), with each pixel represented by a 8- or 16-bit gray scale value. This representation could be so large that it is difficult to store or transmit. The purpose of image compression is to reduce the size of the representation and, at the same time, to keep most of the information contained in the original image. Compression techniques intrinsically fall into two categories: predictive coding and transform coding [1]. The basic idea of predictive coding is to generate an array of uncorrected random variables from the given image by using an invertible transformation. The redundancy that occurs in the neighboring pixels is reduced and the original image can be represented by, relatively, fewer bits. Transform coding, on the other hand, applies an invertible two-dimensional discrete transform to the given image. Only a subset of the transformed coefficients is retained and quantized for further processing. Hybrid image compression techniques combine these two techniques and achieve better result.

Click here for free

## download this paper

**Related**

Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE

Selectively Patterned Masks: Structured ASIC with Asymptotically ASIC Performance

FREE IEEE PAPER

COMMENTthesis, vlsi