ENGINEERING RESEARCH PAPERS

clock gating IEEE PAPER




Power reduction through RTL clock gating
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ABSTRACT This paper describes a design methodology for reducing ASIC power consumption through use of the RTL clock gating feature in Synopsys Power Compiler. This feature causes inactive clocked elements to have clock gating logic automatically inserted

A review of clock gating techniques
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Abstract: The synchronous design operates at highest frequency that drives a large load because it has to reach many sequential elements throughout the chip. Thus, clock signals have been a great source of power dissipation because of high frequency and load. Clock

Reducing switching power with intelligent clock gating
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Clock gating is a well understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires the designers to add a small amount of logic to their RTL code to disable or deselect

Clock gating for power optimization in ASIC design cycle theory practice.
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Page 1. Clock Gating for Power Optimization in ASIC Design Cycle: Theory Practice Introduction Combinational Clock Gating State of the art Open problems Sequential Clock Gating

Effects of different clock gating techinques on design
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Abstract-Low power is one of the most important issues in today's ASIC (Application Specific Intregated Circuit) design. As the transistor is scaled down, power density becomes high and there is urgent need of reduction in power. The clock gating is one of the most elegant and

Automatic clock gating for power reduction
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ABSTRACT As the transistor count and operating frequencies of graphics chips increase, power consumption has become a critical problem in the design of these components. Often the location of these components on a system chassis makes it is difficult to provide

High-level synthesis for minimum-area low-power clock gating
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Clock gating is one of useful techniques to reduce the dynamic power consumption of synchronous sequential circuits. To reduce the power consumption of clock tree, previous work has shown that clock control logic should be synthesized in the high-level synthesis

Clock gating for low power circuit design by Merge and split methods
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ABSTRACT In present VLSI technology energy dissipation is an important factor to be considered among other factors like area, speed and performance in portable devices. The size reduction and complexity of portable devices have resulted in large amount of power

Low power input/output port design using clock gating technique
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Abstract:-Clock gating is a well-known technique to reduce chip dynamic power. This paper propose a modified clock gating techniques based on ACG (Adaptive Clock Gating) and instruction level clock gating. The proposed clock gating technique reduces not only

Design of an ALU with a low power LFSR using Clock gating
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Abstract:This paper proposes a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on data driven clock gating approach and it can offer significant power reduction based on the technological

Dynamic Power Reduction of Digital Circuits by Clock Gating
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Abstract Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all adders. However, the enable functions of clock gate can be further

Low Power Synthesis In Digital Design By Automatic Insertion Of Clock GatingAnd Operand Isolation Cells
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Abstract-This work presents a design and verification of low power and high performance router by using dynamic power reduction technique ie Clock gating and Operand isolation. The power consumption of the presented router is significantly lower than that of a router

Power reduction in CMOS technology by using tri-state buffer and clock gating
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Abstract:In this research paper we have implemented different type of clock gating techniques and proposed technique to reduce power. All the techniques are performed at different technology with temperature, voltage and frequency variation and their Dynamic,

Sub word Partitioning and Signal Value based Clock gating Scheme for Low Power VLSI Applications
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Abstract The low power optimization techniques are very crucial for next generation wireless communication and battery powered signal processing applications. Several low power optimization techniques at circuit level and device level were implemented in past two

Power reduction on clock-tree using Energy recovery and clock gating technique
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Abstract:Power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power clocking schemes are promising approaches for low-power design. We

A Clock-Gating Method for Low-Power LSI Design
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Abstract-This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-

Design of Low Power and High Speed Double Tail Comparator Using Clock Gating Method
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Comparators are the basic elements for designing the modern analog and mixed signal systems. The speed and area is main factors for high speed applications. Various types of dynamic double tail comparators are compared in terms of Delay, Area, Power, Glitches,

Power reduction of a CMOS high speed interface using Clock Gating
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Abstract The evolution of human being consciousness changed the way we look at the world in which we live in. Motivated by economical and environmental issues, the word" efficient" became more relevant in our daily lives. The semiconductor industry, especially for the

Power Optimized Memory Organization Using Clock Gating
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Abstract:This project presents circuit design of a low-power dual port memory. The planned memory uses new techniques to reduce its power consumption. Since memories are accessed sequentially, it adopts a separate address bus for read and writes process. A

Low Power 8, 16 32 bit ALU Design Using Clock Gating
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Abstract:In today's world most of us use one or another sort of portable electronic device, and the major problem we face is the battery backup of device. This problem motivated in design of low power ALU which is the integral of any processor. This paper is an attempt

Dynamic Power reduction of synchronous digital design by using of efficientclock gating technique
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Abstract: Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits. One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In This paper we will present a comparative analysis of existing

Design a reduced power shift register with clock gating
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Abstract:in this paper clock gating technique is presented for low power VLSI (very large scale integration) circuit design. Clock in digital circuits is used for synchronization of various components. Clock power is a major source of dynamic power consumed in synchronous

A Low Power Shift Register Design with Clock Gating
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Abstract: In this paper clock gating technique is presented for low power VLSI (very large scale integration) circuit design. Clock in digital circuits is used for synchronization of various components. Clock power is a major source of dynamic power consumed in synchronous

LOGIC ARCHITECTURE AND CLOCK GATING BASED GUARDED EVALUATION FOR POWER REDUCTION
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Abstract: In this paper, guarded evaluation is a dynamic power reduction technique by identifying sub circuits inputs and kept constant at specific times during circuit operation. In certain condition, some signals within the digital design are not observable at output. So

ALU and Floating Point Optimization using Multi-stage Pipelining and Clock Gating
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Abstract:The objective of this paper is to analyze and compare the limiting factors in ALU design. The fundamental elements of an ALU are the input operands, Arithmetic and Logic Design, CPU schematics, and power dissipation. The time space trade off relates the rate

The Design of Ring VCO by using clock gating in 130 nm CMOS
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Abstract-A genuine modulator constituted on QPSK modulator that is ployed for the confinement of the injection in the modulation of phase along the formulation of clock that is locked in phase. As per the suggested gating of clock a VCO, optimization of absorption

Fully Reused VLSI Architecture for FM0 and Manchester Encoding Techniques with Clock Gating
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Abstract: The dedicated short-range communication (DSRC) is Associate in Nursing rising system to push the keen establishment into our presence. The DSRC benchmarks normally embrace FM0 and Manchester codes to succeed in dcequalization, improving the sign

A NOVEL TECHNIQUE FOR REDUCTION OF POWER LOSS IN FLIP-FLOPS BY USING CLOCK GATING AND POWER GATING
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ABSTRACT Power Dissipation plays a crucial role as development of portable devices as concern. So in this paper we discuss about reduction of Dynamic power and Static power consumption in Flip-Flops, because flip-flops are the major power consumption elements

Clock Gating Based Energy Efficient and Thermal Aware Design For Vedic Equation Solveron 28nm and 40nmFPGA
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Abstract In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra'SunyamSamyasamuccaye'says that if sum of numerator and sum of

Implementation of Dynamic RAMs with clock gating circuits using Verilog HDL
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Abstract--Modern world's major concern is to minimize power consumption by the best way possible. Usage of clock gating technique to minimize dynamic power in sequential circuit is one of the best methods. This paper concentrates on the methods how to restrict the

An Efficient Execution of Clock Gating Technique for Logic Circuits
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Abstract:Clock gating has been heavily used in reducing the power consumption of the clock network by limiting its activity factor. Fundamentally, clock gating reduces the dynamic power dissipation by disconnecting the clock from an unused circuit block. This result in

Performance Comparison of Various Clock Gating Techniques
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Abstract: Clock signal have been a great source of power dissipation in synchronous circuits because of high frequency and load. So, by using clock gating one can save power by reducing unnecessary switching activity inside the gated module. Here four gating

IMPLEMENTATION OF NEW SLANT FOR EFFICIENT POWER SAVING IN DIGITAL DESIGN BY USING AUTOMATIC CLOCK GATING TECHNIQUE
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Abstract-This paper describes about the design methodology for reducing router power consumption with the aid of RTL clock gating technique. It causes inactive clocked elements to have clock gating logic (automatically by using cadence tool) which reduces power

Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating
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Abstract To minimize Power dissipation is one of the major concerns in recent VLSI designing. As technology is growing our chip size is getting reduced and many other micro- electronics reliabilities are growing slowly, minimum power designing of any system has

Hardware Architecture of Low-Power ALU using Clock Gating
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Abstract: With the scaling of technology, need for high performance and more functionality, power dissipation becomes a major bottle neck for microprocessor systems design, because clock power can be significant in high performance systems. We propose a low power

A Novel Low Power Hybrid Clock Gating Technique for High Frequency Applications-Power and Area Analysis
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Abstract: Proliferation of high speed applications is leading towards increase in the dynamic power consumption per chip. Clock gating is found to be the most effective technique by which overall power consumptions can be reduced without sacrificing the performance

A Low Power I/O Port with Clock Gating Design
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Abstract: Clock gating is a well-known technique to reduce chip dynamic power. This paper proposes a modified clock gating techniques based on ACG (Adaptive Clock Gating) and instruction level clock gating. The proposed clock gating technique reduces not only

Algorithmic Level Hardware Design using CoDeL and Automated Clock Gating
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For rapidly prototyping hardware architectures, we have developed a system level design language, called CoDeL (Controller Description Language) .targets the specification and design at the behavioral level. Details of the platform and the language

Clock Gating Based Low Power ALU Design
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Abstract: In this paper, latch based clock gating technique is applied in ALU to reduce clock power and dynamic power consumption of ALU. This technique is simulated in Xilinx14. 7 tool and implemented on 90-nm sparton-3 FPGA. When clock gating technique is not

DESIGN AND IMPLEMENTATION OF 32 BIT ALU USING LOOK AHEAD CLOCK GATING BASED ON FPGA
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Abstract: Any type of digital architecture is modified by using the VLSI technology. In digital systems, clock gating is the best method to reduce consumption of power. As power consumption plays an important role in any integrated circuit. This methodology is mainly

Review on Clock Gating Techniques
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Abstract:this is an era of hand held devices like cellular mobile phones, personal digital assistants and many more. This is possible because of microprocessors embedded in these devices. These devices must operate at high speeds but at the same time must survive

Design of an Ultra Low Power Clock Gating D Flip-Flop Using Quasi-Static Energy Recovery Logic
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Abstract This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously

Design of Low Power Flip-Flop Using Clock Gating and Power Gating
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Abstract: This Paper describes the facility gating duration system that contains of temporal arrangement components like flip-flops, latches and clock distribution network. This paper enumerates power economical style of shift registers victimization D flip-flops alongside

Power Harvesting and Area Efficient Clock Gating Method for a De-Composed MUX Controller.
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Abstract: Multiplexer (MUX) is the key switching element to process and feed the data to various blocks of a computing core. Nowadays the data size is of 64 bit or beyond. The use of MUX in ALU's plays a prominent role to switch the correct logic path to further stage.

Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA
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Abstract In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective

The Optimal Flip-Flop Grouping in Data-Driven VLSI Clock Gating
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A Flip-Flop (FF) grouping problem is arising in the context of clock gating, which is a predominant technique used for power saving in the design of VLSI chips. Due to its hardware overhead, data-driven gating requires that FFs rst be gathered in groups of a

Power Minimization by Clock Gating For Low Power in Microprocessor
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Abstract:Power consumption has become an important factor in low power VLSI design. The need for power saving design has a large potential. Due to advancement in technology in several years there is a vast need of power sensitive designs. There are many power

A Novel Approach for Auto Clock Gating of Flip-Flops
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Abstract: Clock gating is a one of the power saving technique. It is a popular technique used in many synchronous circuits for reducing dynamic power dissipation and extraordinarily helpful for decreasing the ability power wasted by digital circuits. This paper proposes a

Data Driven Clock Gating for Logical Groups in Low Power Applications
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Abstract: In the current scenario of VLSI and other electronics industries it has become imminent to address the three very basic issues namely speed, power and size. In this project the main focus is on the power parameter. Generally synchronous circuits waste a

Clock Gating and Run Time Power Gating Integration by Using Dual Stacking Technique
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Abstract: This Paper describes the facility Gating duration system that contains of temporal arrangement components like flip flops, latches and clock distribution network. This paper enumerates power economical style of shift registers victimization D flip flops alongside

A Review on Clock Gating Methodologies for power minimization in VLSI circuits
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Abstract This research paper gives the introduction of the various clock gating techniques. It also provides the basic clock gating principles, benefits, limitations and enhancements in traditional clock gating scheme. Also it provides the details of parameters which can affect

A Clock Gating Technique Using Auto Gated Flip Flop for Look Ahead Clock Gating
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Abstract: The look ahead clock gating based on auto gated flip flops method combines the previously three methods. Several techniques to reduce the power have been developed of which clock gating is predominant. This look ahead clock gating computes the clock

Power Optimization of I/O Ports Using Clock Gating Technique
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Abstract:This paper deals with the one of the application of clock gating techniques. As we all know that today power and switching speed optimization are the major areas on which vlsi designers are more concern about. Clock Gating Technique is one of the solutions to

A LOOK AHEAD PARTIAL BUS SPECIFIC CLOCK GATING BASED ON AUTOGATED FLIPFLOPS
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Abstract:-The clock gating which could be enables the clock signals from the CDN (clock distribution network). This technique could be activating the clock which is needed for the operation of the circuit. The unnecessary clock signals are not activated during the clock

A Logical Survey on Look Ahead Clock Gating Process
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ABSTRACT Clock gating is incredibly helpful for reducing the facility consumed by digital systems. There are three different types of clock gating. The foremost fashionable is synthesis-based; account clock sanctioning signals supported the logic of the underlying

Integration of Bus Specific Clock Gating and Power Gating
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Abstract: In integrated circuits a gargantuan portion of chip power is mostly consumed by clocking systems which comprises of flipflops, latches and clock distribution networks. The two most widely used techniques for the reduction of dynamic and leakage power are

A COMPARATIVE ANALYSIS OF LOOK AHEAD CLOCK GATING USING 22NM TECHNOLOGY
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ABSTRACT Clock gating is a one of the power saving technique. It is a popular technique used in many synchronous circuits for reducing dynamic power dissipation and extraordinarily helpful for decreasing the ability power wasted by digital circuits. This

Analysis of Clock Gating and Power Gating Techniques on Sequential Circuits
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Abstract: In Integrated circuits a maximum portion of chip power is expended by clocking system which comprises of timing elements such as flip-flops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using D flip-flops

A Novel Algorithm of Clustering for Fine-Grained Clock Gating for Ultra-Low Power Applications
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Abstract: Clock gating has proven to be an effective and widely used technique for reducing dynamic power in VLSI CMOS circuits, especially in register transfer level (RTL). In this paper, we propose a low-power algorithm that considers the switching activity of flip-flop (

POWER OPTIMIZED DATAPATH UNITS OF HYBRID EMBEDDED CORE ARCHITECTURE USING CLOCK GATING TECHNIQUE
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ABSTRACT Minimizing power consumption is a primary consideration in hardware design of portable devices where high performance and functionality is required with limited battery power. With the scaling of technology and the need for high performance and more

An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating
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Abstract: In this paper, a new method for minimizing power dissipation in 4-bit Johnson up- down counter is proposed. In this design, we have used a dual dynamic pulsed flip-flop (DDFF)[1], which supports embedding a logic module (DDFF-ELM) and a power saving

Analysis of Modified Energy Recovery Flip Flops with Clock Gating
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Abstract:Power dissipation has become an important factor while designing the circuits these days. Flip flops are the basic storage element in most of the digital electronics circuits like laptop, mobile, microprocessor, washing machine, microwave etc. So, energy

Low Power Register Design with Integration Clock Gating and Power Gating
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ABSTRACT In Integrated circuits a gargantuan portion of chip power is expended by clocking system which comprises of timing elements such as flip-flops, latches and clock distribution network. This paper enumerates power efficient design of shift registers using

Dynamic Power Reduction in Linear Feedback Shift Register Using Look AheadClock Gating Technique
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(LFSR) with Look Ahead Clock Gating (LACG) technique is presented to reduce the power consumption in sequential circuits. Clock gating is a predominant technique used to reduce unwanted switching of clock signals. Several clock gating techniques to reduce the

Design of a Novel Glitch-Free Integrated Clock Gating Cell for High Reliability
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3.1 Gated clock from latch-AND based ICG cell when En has glitches. 13 3.2 Gated clock from latch-NOR based ICG cell when En has glitches. 14 3.3 Gate level schematic of the proposed ICG cell. 15 3.4 Gated clock of the proposed ICG cell when En has glitches.

Low Power Crypto Core Design Using Clock Gating
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Abstract: This paper discusses the efficient usage of the Advance Encryption Standard (AES) that will be used to implement high secured and low power Crypto design by using clock gating technique. Clock gating technique is simple and effective method to reduce power

TECHNOLOGY REDUCING POWER DISSIPATION IN SELF STARTING AND SELF CORRECTING COUNTER USING A LOOK-AHEAD CLOCK GATING
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ABSTRACT In this paper, a novel Self-starting and Self-correcting counter implemented with some techniques are presented to reduce the power consumption in sequential circuits. Clock gating is a predominant technique used to reduce unwanted switching of clock

A Study Regarding the Implementation with VHDL of a Multiple Clock GatingScheme for Low Power RTL Design
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Abstract-In this paper we propose an algorithm, implemented with VHDL language in RTL design, capable of reorganizing the f1ip-flops from within a circuit in order to reduce the power consumption through optimal c10ck distribution. Practically in the end, starting from

A Comparative Study and Review of Different Clock Gating Techniques and their Application
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Abstract: With the increasing applications of electronics in day-2-day life and alteration in design techniques in the field of VLSI, we are required to design the ICs with maximum efficiency. By efficiency, here we mean the power consumption, the delays, operation at

Design and Analysis of 4 Bit Johnson Counter Using Clock Gating
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Abstract In VLSI design the reduction of power is an important criterion. The performance of a system mainly depends on the method of designing of various blocks of that system. To provide an efficient and meaningful architecture of a VLSI chip, a devoted design is

Design and Implementation of 32 Bit ALU Using Look Ahead Clock Gating Logic
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Abstract–Any type of digital architecture is modified by using the VLSI technology. In digital systems, clock gating is the best method to reduce consumption of power. As power consumption plays an important role in any integrated circuit. This methodology is mainly

Clock Gating Based Low Power Energy Efficient Gurmukhi Unicode Reader Design on FPGA
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(HPEEC), the focus of research is shifting toward energy efficient computing or low power VLSI design or green computing. We are applying three different clock gating technique in target design of Gurmukhi Unicode Reader (GUR). These power saving techniques

Power Reduction with FlipFlop Grouping in Data Driven Clock Gating
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Abstract:In digital circuits Clock signal is one of the factor causing dynamic power consumption. Clock Gating is a method applied for reducing the dynamic power dissipation in sequential circuits. Here the redundant clock pulses in a high frequency clock signal are

CASE STUDIES ON CLOCK GATING AND LOCAL ROUTING FOR VLSI CLOCKMESH
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Page 1. CASE STUDIES ON CLOCKGATING AND LOCAL ROUTING FOR VLSI CLOCK MESH A Thesis by Major Subject: Computer Engineering Page 2. Case Studies on ClockGating and Local Routing for VLSI Clock Mesh Copyright 2010 Sundararajan Ramakrishnan

An Efficient Clock Gating Logic Using Matching Technique
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Abstract:Gate level clock gating establish with netlist. So that it constraints much amount of power across flip-flop and gates. Circuit size enlarge complexity so that it attains execution speed is low. This paper dealt with conquers of these shortcomings by matching

Low Power Design of Digital Systems Using Energy Recovery Clocking andClock Gating
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Clock signals are synchronizing signals that provide timing references for computation and communication in synchronous digital systems. Traditionally, the demand for high performance was addressed by increasing clock frequencies with the help of technology

Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew Clock Gating
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Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew ClockGating Critical-PMOS-Aware Clock Tree Design Methodology for Anti-Aging Zero Skew ClockGating Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan Page 2.

Implementation of a Low Voltage Low Power Double Tail Comparator usingClock Gating
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Abstract: Comparator is fundamental building block in analog-to-digital converters. CMOS comparator which has dual input, dual output inverter stage suitable for high speed analog- to-digital such as flash pipeline ADCs require high-speed with small chip area low voltage

Comparative Analysis of Existing Clock Gating ALU
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Abstract-Digital world multimedia and DSP based applications work on certain clock pulse and as we know, clock signal. The clock signal consumes maximum applied power and this is a major drawback in digital synchronous circuit. Clock gating is an important technique

Dynamic Power Reduction In Energy Efficient Synchronous Circuits UsingClock Gating
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Abstract:Major source of dynamic power consumption in synchronous circuits is clock. Clock in synchronous circuits controls the functioning of circuit by providing signal which