CMOS Low Power Analog Circuit Design-book chapter
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CMOS Low Power Analog Circuit Design-book chapter



This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is shortly presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.
The current trend towards low-power design is mainly driven by two forces [1]: the growing demand for long-life autonomous portable equipment, and the technological limitations of high-performance VLSI systems. For the first category of products, lowpower is the major goal for which speed and/or dynamic range might have to be sacrificed. High speed and high integration density are the objectives for the second application category, which has experienced a dramatic increase of heat dissipation that is now reaching a fundamental limit. These two forces are now merging as portable equipment grows to encompass high-throughput computationally intensive products such as portable computers and cellular phones. The most efficient way to reduce the power consumption of digital circuits is definitely to reduce the supply voltage, since the average power consumption of CMOS digital circuits is proportional to the square of the supply voltage. On the other hand, the reduction of the supply voltage is also required to maintain the electric field at an acceptable level. The resulting performance loss can be overcomed for standard CMOS


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