Demonstration of Integrated Micro Electro Mechanical-MEMS-Relay Circuits for VLSI Applications
presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays’ electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
ALTHOUGH CMOS technology scaling has historically enabled significantly reduced energy-per-operation in integrated circuits, today’s designs are increasingly power limited in ways that technology scaling cannot alleviate. This has occurred because the threshold voltage of the transistors has already been scaled to the value that optimally balances leakage energy and dynamic energy, and hence further reductions in the threshold voltage would actually increase the amount of energy consumed per operation. With the threshold voltage pinned because of sub-threshold leakage, further supply voltage scaling comes at the expense of per-core performance, forcing a trend towards increasingly parallel circuit implementations as the only means to efficiently improve throughput. Unfortunately, even this parallelism will eventually become ineffective as each CMOS functional unit approaches its throughput-independent, minimum achievable energy. The minimum energy in CMOS is limited by the sub-threshold leakage of the transistors because once CMOS circuits enter the sub-threshold regime, an increase in the threshold voltage decreases the leakage current by exactly the same amount that it increases the delay. The only mechanism left to tune both the leakage and dynamic energy components is therefore the supply voltage, which cannot be reduced below a certain value (set by and the circuit’s activity factor and logic depth) without increasing the total energy [1]. If a device with significantly improved leakage characteristics (i.e., steeper sub-threshold slope) were available, major improvements in energy efficiency over CMOS could be achieved [2]. Many researchers have therefore been exploring new switching device concepts to achieve sub-threshold slopes steeper than the limit set by in field-effect or bipolar-junction transistors [3], [4]. However, many of these devices achieve sharp sub-threshold slope over only a limited range of supply voltage, leading to relatively poor on-to-off current ratios and/or very low on-state current at low supply voltages. In this context, micro-electro-mechanical (MEM) relays appear very attractive, having recently demonstrated on-to-off current ratios of ten orders of magnitude over input swings of one millivolt and immeasurably low leakage currents [5]. These relays are four-terminal devices that are functionally similar to CMOS transistors. Despite their nearly ideal I-V characteristics, the time required to mechanically switch a relay from the off- to the on-state is significantly longer than the electrical switching delay of an equivalent CMOS device. Specifically, relays fabricated in a 90 nm technology node are predicted to have delays of 10’s of nanoseconds compared to 100’s of picoseconds for transistors in a threshold optimized CMOS process operating in the sub-threshold regime, or up to nanoseconds in a more generically available CMOS process. Although the large mechanical delay of MEM relays suggests that MEM relay circuits would have very poor performance, we have proposed circuit architectures that significantly mitigate this by implementing logic as large, complex gates that minimize the number of mechanical delays on the critical path
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