Design and Implementation of a Fuzzy Inference Engine on an FPGA-thesis
Fuzzy Logic, which was developed in early 1960s, provides a tool to deal with uncertainty and human reasoning. The main characteristic of a fuzzy logic is the capability to express the knowledge in a linguistic way. Fuzzy Logic empowers the digital designer with the ability to use non-linear controllers for their applications. Fuzzy Logic is used to control systems, whose mathematical model is unknown or time varying, or that require human experience. Fuzzy systems are also used for controlling highspeed systems, and for processing of large volumes of data where enormous amount of computational speeds are required. High computational speeds may be achieved when these systems are realized on a digital hardware. Computational speed of a digital hardware can be increased either by having parallelism or reducing computational complexity or both. Since a digital system works on a reference clock, the computational speed will also depend on the speed grade of the digital system. A simple single-bit full adder requires ten to fifteen gates for sum and carry. Hence implementation of fuzzy logic on a digital platform requires tens of thousands of gates. These gates should be connected in such a fashion that the user has to just fuse the unwanted connection between the gates, to implement the logic easily. Another important feature this pile of logic gates is that the propagation delay has to be considerably low. All the above requirements can be achieved by using a Field Programmable Gate Array (FPGA). The work focuses on how computational complexity of the inference engine can be reduced and the speed of computation can be increased. FPGA is an array of digital gates arranged in such a fashion that the user can logically synthesize his design on to it. These blocks of gates are configured as per the users requirements or programmed at the field so as its name. The user can use VHSIC Hardware Description Language (VHDL) as a tool to design his requirements. Fuzzy controllers are traditionally implemented on FPGA using Look-up Tables (LUT). In this approach, output values are pre-computed for every input value and stored in the RAM. In this case the inference speed is high but there is an exponential growth of IIIthe required memory, if the number of input and output variables or the resolution increases. Alternate way is to store the membership values of the input in an LUT. These LUTs are generally implemented on an external SRAM, which can cost a time delay for accessing its contents. This increases the access times. Another important drawback of the fuzzy controllers is the computational complexity of the defuzzification part because the defuzzification part involves arithmetic division operation. Usually to get away from this bottleneck, the defuzzified output values are pre-calculated and stored in an EPROM. The above discussed pre-computation however requires some techniques for calculating the output. A modified algorithm is proposed to reduce the computational complexity of the defuzzification part by removing the arithmetic division operations. This is achieved by enforcing some constraints on the fuzzy subsets. As constraints are imposed on the fuzzy sets, the proposed system brings in difficulties in designing a real-world problem. As the real-world problems are non-linear, the system requires a non-linear mapping. The membership functions of the system is implemented using LUTs but using the internal memory of the FPGA, thereby reducing the access time. We use the Embedded Array Block (EAB) memory to implement FIE, thereby reducing the memory access time. The proposed design requires less pre-computation than the existing methods. The fuzzy controllers also have a computational complexity due to multiplication. The number of bits used for membership function is reduced from 7 bit to 4 bit, which reduces the computational complexity and also the space used for LUT. Fuzzy controller for various types of problems like first order system, thermal process and inverted pendulum is explored using the designed FIE. The work demonstrates how the computational power, speed of computation and the reconfigurability of FPGA aids in building Fuzzy Inference Engine for various types of systems. When moving towards an adaptive control domain, the work demonstrates how an auto-tuning algorithm can be implemented for a process control problem using an FPGA. The auto-tuning algorithm itself uses a fuzzy system for tuning the scaling factors of the parent fuzzy logic controller. The parent fuzzy logic controller controls the plant. The auto-tuner modifies the scaling factors of the fuzzy controller. The results are quite satisfactory. IVA real-time plant is required to test the designed FIE. Hence, a platform has been designed been designed for performing the real-time testing. The designed FIE is connected through the ADC/DAC to a simulated plant in MATLAB. It interacts with the Advantech PCI-1711 12-bit ADC-DAC Data Acquisition System (DAS) to send and receive data from the FIE. This way of experimental implementation of the system using a MATLAB platform offers the flexibility of complete developmental testing of the FIE, after which, the FIE can be detached and directly connected to plant’s sensors for realtime control. Computational speed ranging from 2.5 M Fuzzy Logical
Free download research paper
CSE PROJECTS