Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE
Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm radix-4- based 8 parallel turbo-decoder ASIC in 0.13 m CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.
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Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
AN ASIC IMPLEMENTATION OF THE TWO-DIMENSIONAL DISCRETE COSINE TRANSFORM
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