Design of Low Power Analog Drivers Based on Slew Rate Enhancement Circuits for CMOS Low-Dropout Regulators
Low-power analog driver based on a single-stage amplifier with an embedded current-detection slew-rate enhancement (SRE) circuit is presented. By developing a systematic way to design both the response time and optimal sizing of driving transistors in the SRE circuit, the SRE circuit can be controlled to turn on or turn off properly. In addition, the analog driver only dissipates low static power and its transient responses are significantly improved without transient overshoot when driving large capacitive loads. Implemented in a 0.6- m CMOS process, a current-mirror amplifier with the current-detection SRE circuit has achieved over 43 times improvement in both slew rate and 1% settling time when driving a 470-pF load capacitor. When the proposed analog driver is employed in a 50-mA CMOS low-dropout regulator (LDO), the resultant load transient response of the LDO has 2-fold improvement for the maximum load-current change, while the total quiescent current is only increased by less than 3%.
I N RECENT years, low-dropout linear regulators (LDOs) are widely used in the portable battery-powered electronic devices as LDOs can convert decaying battery voltages to lownoise and accurate voltages for noise-sensitive systems. Since integrated CMOS LDOs only occupy small chip area, they are also adopted to power up sub-blocks of a system individually in the system-on-a-chip designs in order to tackle the crosstalk problem . Both board space and external pins can be minimized. The design of high-performance CMOS LDO is thus necessary. In LDO design, large gate capacitance of power transistor degrades the loop-gain bandwidth and the slew rate at the gate drive of the LDO in low-power condition. Both low quiescent current and fast load transient response, therefore, cannot be achieved simultaneously by using the generic LDO structure. To address this problem, a voltage buffer/driver can be inserted Fig. 1. Structure of LDO with the proposed analog driver. between the error amplifier and the power transistor. The voltage buffer should improve both the loop-gain bandwidth and slew rate at the gate drive of the power transistor, while the buffer dissipates small quiescent current in the static state . However, it is difficult to realize a good voltage buffer to meet the requirements perfectly in practice. This paper presents a new current-efficient analog driver for the CMOS LDO. The proposed analog driver is implemented by a single-stage amplifier (core amplifier) in noninverting unitygain configuration with an embedded slew-rate enhancement (SRE) circuit as shown in Fig. 1. The paper is organized as follows. Section II addresses the design considerations of the proposed analog driver. Operating principle, systematic design method and circuit implementation of the current-detection SRE are discussed in Section III. Results of the analog driver and its application to LDO are shown in Section IV to justify the functionality of the proposed analog driver. Finally, conclusions are given in Section V.
Free download research paper
CSE PROJECTS