Fault modeling and simulation using VHDL-AMS-vlsi
Fault modeling and simulation using VHDL-AMS
Abstract. Fault simulation is an accepted part of the test generation procedure for digital
circuits. With complex analog and mixed-signal integrated circuits, such techniques must now
be extended. Analog simulation is slow and fault simulation can be prohibitively .
An object-oriented view of structural VHDL description
An evolutionary approach to automatic generation of VHDL code for low-power digital filters
FREE IEEE PAPER