fpga-field programmable gate arrays-research papers-2012 section 6

fpga-field programmable gate arrays-research papers-2012 section 6





Implementation of Color image Enhancement on FPGA using HSV
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VKR Asha, S Kumar ,irnetexplore.ac.in ABSTRACT This paper presents the implementation of color image enhancement using HSV color space. An efficient architecture is designed for Histogram Equalization (HE). Geometric mean filter is used to make sure image details such as edges and sharpness are

Sobel Edge Detection using Parallel Architecture based on FPGA
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V Sanduja, R Patial ,research.ijais.org ABSTRACT This paper proposes an FPGA based approach known as Sobel Edge Detection. RGB image is taken by the computer source and converted into binary image using MATLAB. The proposed Sobel Edge Detection is modeled using Parallel

From Control Design to FPGA Implementation
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M Mller, HC Schwannecke, W Fengler ,cdn.intechopen.com As a modelling and simulation tool, MATLAB/Simulink plays a significant role in industrial control design. To allow the deployment of the designed control solutions a number of code generation facilities have been developed, that aim on implementing PC-based control

A Low Power Asynchronous FPGA with Power Gating and LEDR Encoding
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K Naveena, N Kirthika ABSTRACT In this paper a low power Asynchronous FPGA is designed. Power gating technique is used in this paper which reduces power. The type of Power Gating used is Fine Grain Power Gating. In fine grain power gating, each LUT has its own sleep transistor and

FPGA Based Longitudinal and Lateral Controller Implementation for a Small UAV
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ABSTRACT This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems.

Implementation of Multi-User FPGA Environment Over TCP/IP
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SD Pansare, SM Turkane ABSTRACT Optimizing the single target device as a simulator in a multi user environment is our aim to achieve. It is important step to use FPGA to design and improve flow of multi user data in a high speed computer network environment. Hence, we create a system where

FPGA Based Hardware Efficient Digital Decimation Filter for?-? ADC
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SK Maity, HS Das ,signal processing ABSTRACT This paper focuses on the design of a FPGA based off chip digital decimation filter for single bit sigma-delta A/D converter with medium oversampling ratio for the processing of audio signal. A second-order single-stage sigma-delta (?-?) modulator with single bit

FPGA Architecture
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D Markovic ,icslwebs.ee.ucla.edu ? Single/dual-port 32x1bit RAM? Quad-port 32x2bit RAM? Simple dual-port 32x6bit RAM? Single/dual-port 64x1bit RAM? Quad-port 64x1bit RAM? Simple dual-port 64x3bit RAM? Single/dual-port 128x1bit RAM? Single-port 256x1bit RAM? 32-bit shift register

FPGA-BASED CONTROL OF THERMOELECTRIC COOLERS FOR LASER DIODE TEMPERATURE REGULATION
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A ALI, C ALAOUI ABSTRACT The proportional-integral-derivative (PID) controller is the most used controller in the industry. Field programmable gate arrays (FPGAs) allow efficient implementation of PID controllers. This paper presents the temperature regulation of a 48W laser diode through

Power/Performance Optimization in FPGA-Based Asymmetric Multi-Core Systems
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B de Abreu Silva, V Bonato ,fpl2012.project.ifi.uio.no Conclusion We believe this work has a significant potential to optimize the relation between power and performance for multi-core platforms. In the proposed tool, new power-aware mapping and scheduling algorithms are explored as well as their integration with the

AN ARTIFICIAL EYE FOR THE BLIND PEOPLE USING FPGA TECHNOLOGY
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ABSTRACT Till date blind people struggle a lot to live their miserable life. Their problems have made them to lose their hope to live in this competing society. They seek help from others to guide them whole day. This project aims to make the blind person fully

MINIMIZING THE FIR FILTER AREA USED IN A FPGA POWER COMPUTING INSTRUMENT
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C DAMIAN, C ZET, AP Eng, E DANILA ,power ,agir.ro ABSTRACT. Instrumentation is essential in any domain. The paper presents an instrument for simultaneous active, reactive and apparent power measurement. The instrument is implemented on a field programmable gate array (FPGA) device. The instrument is fitting

A New Platform and Methodology for System-Level Design of Next-Generation FPGA-based Digital SMPS
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ABSTRACT Increasing adoption of FPGAs in digital switched-mode power supply (SMPS) control is driving significant interest in improved platforms for development and commercial deployment. A new methodology for high-level system design of SMPS controllers is

Real-Time Implementation of Automatic Road Extraction for High Resolution Satellite Images Using FPGA
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V Parthasarathi, DY Pushpamitra ,gjitcs.com ABSTRACT Analysis of high resolution satellite images has been an important research topic for urban analysis. One of the important features of urban areas in urban analysis is the automatic road network extraction. Two approaches for road extraction based on Level

Cryptographic Unit of Embedded Processor in FPGA Implementing for Speed and Security
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ABSTRACT Networking and data communications security has become a vital requirement since the emergence and common use of computer networks. The main goal of this presented work is to implement the RSA symmetric cryptography algorithm and ECC in

Field programmable gate array (FPGA) realization of a fast 2-D discrete cosine transform algorithm for higher image compression
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MS Islam, MS Bhuyan, MR Sarker, M Othman This paper describes the field programmable gate array (FPGA) implementation of a fast 2-D discrete cosine transform (DCT) chip for higher image compression ratio. The development of encoding and decoding parts of 2-D DCT algorithm is carried out by using Matlab

FPGA Implementation of 64 Point FFT for Passive RADAR Applications
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ABSTRACT A power efficient Fast Fourier Transform (FFT) processor for use in the Direction of Arrival (DOA) estimation of a wideband waveform is presented. The target device for implementation is a Xilinx Spartan-3 Xc3s200 Field Programmable Gate Array (FPGA).

Implementation of Parallel DA Technique for DWT-IDWT on FPGA for Image Compression
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KB Sowmya, S Sonoli, M Nagabushanam ABSTRACT Due to the increasing traffic caused by multimedia information and digitized form of representation of images, image compression become a necessity. The Parallel Distributive Arithmetic (DA) architecture has a reduced latency and a good throughput.

An Optimization of the FPGA Based Wavelet Trigger in Radio Detection of Cosmic Rays
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Z Szadkowski ,fedcsis.org ABSTRACT For the observation of ultra high-energy cosmic rays (UHECRs) by the detection of their coherent radio emission an FPGA based wavelet trigger is being developed. Using radio detection, the electromagnetic part of an air shower in the atmosphere may be

FPGA based sigma–Delta analogue to digital converter design
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PA Uchagaonkar, SA Shinde, VV Patil, RK Kamat ABSTRACT This paper reports design and development of modified Sigma-Delta ADC realized in FPGA paradigm. The wide gain of this ADC makes it a potential candidate in data converter applications in wide ranging domains such as communication systems,

Embedded Web Server using Soft Processor on FPGA Platform
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VM Selvi, K Rathnakannan ABSTRACT This paper describes the design of Embedded Web Server on Soft core, a configurable RISC processor available on Spartan 3a FPGA kit. An Embedded Web Server is used to monitor and control embedded application using any web browser. Embedded

A High Throughput and Memory-efficient Regular Expression Matching on FPGA?
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ABSTRACT Regular expression matching engine is a key component in many content inspection based network applications. But it is facing two issues: low speed and state explosion. In order to address these issues, we propose a novel architecture for high

FPGA Based Pipelined Implementation of Fast 2-D 4 4 Inverse Transform of H. 264
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ABSTRACT Integer transformation is used to exploit the spatial redundancy of input video in the recent video coding standard H. 264. In this paper, a pipelined architecture of fast 2-D inverse transform for H. 264 is proposed. For video compression applications such as

EFFICIENT HANDLING OF SYNAPTIC UPDATES IN FPGA-BASED LARGE-SCALE NEURAL NETWORK SIMULATIONS
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Abstract We present novel methods for handling synaptic updates in FPGA-based neural network simulations that are designed to makes efficient use available memory and to allow for real-time simulation of large numbers of neurons and synapses. Our methods allows

Design of Custom Processors for the FPGA Devices
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ABSTRACT. Programmable devices in the Field Programmable Gate Array (FPGA) technology enable design and prototyping implementation of complex digital systems executing their tasks on central processing units (CPU) and application-specific logic components. The

Modeling and Simulation of Data Encryption Standard Algorithm on FPGA
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ABSTRACT In this paper we demonstrate an efficient and compact reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. Our design was implemented on FPGA of device VirtexEXCV400e. As a strategy to reduce the associated

FPGA Implementation of 4-D DWT and BPS based Digital Image Watermarking
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ABSTRACT In order to protect copyrighted material from illegal duplication, two typical technologies have been developed they are key-based cryptographic techniques and digital watermarks which enable the appropriate security during the transmission process. A

An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication Systems
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ABSTRACT FPGA-based prototyping is nowadays common practice in the functional verification of hardware components since it allows to cover a large number of test cases in a shorter time compared to HDL simulation. In addition, an FPGA-based emulator

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