fpga-field programmable gate arrays-research papers-2012 section 7

fpga-field programmable gate arrays-research papers-2012 section 7




Proposed Low-Power FPGA Architecture Using an Autonomous Fine-Grain Power Gating
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M Kiruthiga, LMIL Joseph ABSTRACT FIELD-PROGRAMMABLE gate arrays (FPGAs) are widely used to implement special-purpose processors. FPGAs are economically cheaper for low quantity production because its function can be directly reprogrammed by end users. FPGAs consume high

IMPLEMENTATION OF DIGITAL FILTERS IN FPGA STRUCTURES
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M Ferenc-Emil, GS Zoltn ,scientificbulletin.upm.ro ABSTRACT Filtering is the most common task in digital signal processing, when some particular parameters of the input signal are removed or modified and a new signal is obtained at the output. The most common filtering goal is to remove noise from a signal.

FPGA based FFT Algorithm Implementation in WiMAX Communications System
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KS ASHA, G MOHAN Abstract Increasing the performance is the best criterion for developing any communication system. The work presented here is aimed at increasing the speedperformance of the OFDMA (Orthogonal Frequency-Division Multiple Access) modulator and demodulator.

IEEE demonstrator on FPGA
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ABSTRACT Embedded instruments gain importance as fault management and fault tolerance mechanisms become essential feature in complex modern semiconductor devices. The upcoming DfT standard, IEEE P1687 IJTAG is designed to provide means of accessing

A Modular Transform Method of Crypto Algorithm for Optimized FPGA Synthesis
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D Kim, HW Choi ,20 ABSTRACT This paper describes optimization methodology of FPGA implementation of crypto algorithm in embedded system. In USN (Ubiquitous Sensor Network) or Ubiquitous computing environment, security is taken accounted of as important element in

Development of an Instrumentation System Embedded on FPGA for Real Time Measurement of Mechanical Vibrations in Rotating Machinery
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C esar da Costa, M Kashiwagi ,professorcesarcosta.com.br ABSTRACT The real-time monitoring of events in an industrial plant is vital, to monitor the actual conditions of operation of the machinery responsible for the manufacturing process. A predictive maintenance program includes condition monitoring of the rotating machinery,

FPGA Implementation of A MIPS RISC Processor
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VN Sireesha, DHH Santosh ABSTRACT This project targets the implementation design of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using VHDL (Very high speed integrated circuit Hardware Description Language). In this paper

Broadband Mobile Communication in MIMO-OFDM With FPGA Implementation Using 200MHz Transmitter And Receiver Using i-MAT Antenna Technology
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ABSTRACT This paper focuses on Implementation and Optimiza-tion of Multiple Input and Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) system using Space Time Block coding (Alamouti Technique) with its Implementation in FPGA. In this we

FPGA based control and monitor for CBM-TOF-readout
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C Xiang, N Herrmann, I Deppner, PA Loizeau ,140.181.64.223 As the CBM experiment will apply a free streaming data acquisition system, the system will be exposed to a potentially very high data rate with like in the case of noisy channels. In order to suppress useless data as soon as possible to prevent bottle-necks in readout

Integrating Timing and Positioning Algorithms onto a Single FPGA Platform for Positron Emission Tomography
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ABSTRACT Previous research at the University of Washington has developed methods to accurately extract coincidence timing and positioning information from an incoming digitized pulse stream within an FPGA. Up to this point, the timing and positioning

FPGA BASED IMPLEMENTATION OF DOUBLE PRECISION FLOATING POINT ADDER/SUBTRACTOR USING VERILOG
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ABSTRACT Floating Point operations is widely used in many areas, especially in signal processing. The greater dynamic range and lack of need to scale the numbers makes development of algorithms much easier. However, implementing arithmetic operations for

FPGA Implementation of Elliptic Curve Cryptography Engine for Personal Communication Systems
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MBI REAZ, J JALIL, H HUSIAN, FH HASHIM ,aa ,wseas.org ABSTRACT Elliptic Curve Cryptography (ECC), which allows smaller key length as compared to conventional public key cryptosystems, has become a very attractive choice in wireless mobile communication technology and personal communication systems. In this research,

IIR filters using Xilinx System Generator for FPGA Implementation
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HV Dixit, V Gupta ABSTRACT This paper proposes the implementation of IIR filter using Xilinx System Generator software on an FPGA. While designing any digital filter, the overflow and quantisation effects must be considered for stability. The speed of computation is greatly increased by

An FPGA Based Deign and Implementation of Digital Pulse Compression Circuit for Barker Code
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TR Saed, MA Al-Mashhdini, HM Al-Ethawi ABSTRACT This paper describes the real time generation of the Barker code pulse compression using Field Programmable Gate Array (FPGA), which is provides the flexibility of reconfigurability, capacity, accuracy and processing of echo signal with or by low cost

Electromagnetic Side-channel Attack against 28-nm FPGA Device
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Y Hori, T Katashita, A Sasaki, A Satoh ,isaa.sch.ac.kr ABSTRACT. Correlation-based electromagnetic analysis (CEMA), a type of sidechannel attack (SCA), is conducted on the latest 28-nm field-programmable gate array (FPGA) device. SCA exploits physical information leakage from a cryptographic device such as power

FPGA Design and Synthesis of Reconfigurable OFDM Transceivers for SDR
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S Prabu, E Logashanmugam ABSTRACT This paper presents a software-defined radio (SDR) system with reconfigurable architecture for wireless communications. The baseband software implementation by using a low-power fixedpoint digital signal processor (DSP) is applied to demonstrate the

Implementing SHA-224/256 Algorithm for Secure Commitment Scheme Applications usingFPGA
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VVS Karthik, TV Sridhar ,irnetexplore.ac.in ABSTRACT This paper uses the similarity between SHA-224 and SHA-256 algorithms to design the SHA-224/256 IP core oriented Digital Signature. The IP core uses parallel structure and pipeline technology to simplify the hardware design and improve the speed by 26%.

An Implementation method of Encrypting Partial Bitstream Based on FPGA
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A Kumar, K Gaurav, A kumar Gautam ABSTRACT Partial reconfiguration of FPGAs requires loading partial bitstream. But loading a faulty or corrupted partial bitstream might cause some errors when undergoing reprogramming; what s more, it may damage the FPGA device. A encrypt method based

FPGA based ON-Line UPS using PWM Technique
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C Senthilsingh, M Manikandan ABSTRACT This paper presents a Xilinx Field Programmable Gate Array (FPGA) based ON- line UPS Using PWM Technique. Xilinx FPGA is a programmable logic device developed by Xilinx which is considered as an efficient hardware for rapid prototyping. It is used to

DWDM Optical Supervisory Channel by Manchester Code on FPGA
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H Borhanifar, A Poureslami, SA Alavian ABSTRACT The next generation optical wavelength division multiplex (WDM) network will transport a stupendous aggregate data rate that consists of all existing types of payload, synchronous and asynchronous, and all types of traffic, voice, video and internet. The

Bus Monitor Implementation for MIL-STD 1553B protocol with FPGA device and PC connectivity.
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C Prez, M Principi, A Principi, D Fusari1 Sr, D Badino ,argencon.org.ar Resumen-En el presente trabajo se describe la implementación, mediante la utilización de FPGA y elementos COTS de un equipo que permite realizar el monitoreo del trfico presente en un bus Muxbus sobre el cual se utiliza el protocolo MIL-STD-1553B. Si bien

FPGA Implementation of a New Parallel FIR Filter Structures
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ABSTRACT In recent days filters with large lengths are started to use. So parallel processing is essential at any cost. In this paper proposes new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the

FPGA Implement of a Vision Based Lane Departure Warning System
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YR Lin, YF Su ABSTRACT Using vision based solution in intelligent vehicle application often needs large memory to handle video stream and image process which increase complexity of hardware and software. In this paper, we present a FPGA implement of a vision based lane

DESIGNING AND SIMULATION OF BAND-PASS INFINITE IMPULSE RESPONSE DIGITAL FILTER USING FPGA DEVICES
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M WIJAYANTI, A HAKIM, SA SUDIRO ,irnetexplore.ac.in ABSTRACT In this article, the filter design is presented. The first step is specifying the filter specifications, perform mathematical calculations band-pass IIR filter, simulated the design calculation results using MATLAB and finally implemented the design using FPGA. Direct-

FPGA BASED ON ADAPTIVE FUZZY AND SPACE VECTOR PULSE WIDTH MODULATION TO CONTROL SPEED OF PMSM
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NV Quynh, T Hanh, TTT Tam ,kc.lhu.edu.vn ABSTRACT This paper presented speed control algorithm of Permanent Magnet Synchronous Motor (PMSM) basing on adaptive fuzzy combined with space vector pulse width modulation (SVPWM). PMSMs were applied so much in manufacturing industry such as metal cutting

Dynamically Reconfiguring through Phase Detection on FPGA
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Abstract Previous researches have shown some approaches on hardware phase detection. In this work, we propose a new framework based on Xilinx Virtex-6 platform for the implementation of task-optimized coarse-grained reconfiguration that can be reconfigured

An evolutionary algorithm based distributed charge management system for electric vehicles realized with FPGA
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M Mielke, A Grnewald, R Brck In the last years, different car manufacturers presented battery electric vehicles and plug-in hybrid electric vehicles with ranges of more than 100 km, making them usable for the most daily tasks. Combined with the high prices for fossil fuels, battery electric vehicles and

FPGA Implementation On Reversible Floating Point Multiplier
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M Jenath, V Nagarajan ,International Journal of Soft Computing ABSTRACT Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of

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