HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFECT TRANSISTOR
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
Over the past years, silicon-based electronic technology has been improved through downscaling MOSFETs, resulting in higher device performance and density. However, there are still some obstacles to scaling, such as diffusion areas will no longer be separated by a low doped channel region and equivalent gate oxide thickness will fall below the tunnelling limit. Hence, it is important to extend or complement traditional silicon technology. As one of the promising technologies, nanotechnology avoids most of the fundamental limitations for conventional silicon devices. Nanoelectronic is an applicable field of nanotechnology that is producing nanoscale machines and systems efficiently, such as nanowires, nanoparticles and Carbon Nano Tubes (CNT). CNTs have special electronic, thermal and mechanical properties that make them attractive for the future integrated circuit applications. Transistors with carbon nanotubes as their channel are called Carbon Nanotube Field Effect Transistor (CNFET). Recently, some circuit applications are presented based on CNFETs, such as ring oscillators, invertors, and logic gates [1]. Arithmetic operations are extensively used in many VLSI applications such as signal processing, and digital communications [2], [3]. Adders are major part of computational circuits that are used for implementing any other arithmetic operation such as subtraction, multiplication or even logarithmic functions [4],[5]. Hence, efficiency of Adders affects performance of whole system therefore designers attempt to produce more efficient Adders. Many logic styles have been designed since now to produce efficient Full Adder cells. The complementary CMOS and CPL designs are two conventional Adders based on CMOS structure. Based on transmission function and transmission gate, TFA and TGA designs were implemented. The other designs are classified as Hybrid designs. Applying
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A high speed 8 transistor full adder design using novel 3 transistor XOR gates
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The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been
Comparative Performance Analysis of XORXNOR Function Based High Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
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This paper presents comparative study of high speed low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called XOR (3T) is
New design methodologies for high speed mixed-mode cmos full adder circuits
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This paper presents the design of high speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also
High speed NP-CMOS and multi-output dynamic full adder cells
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In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using
High speed gate level synchronous full adder designs
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Addition forms the basis of digital computer systems. Three novel gate level full adder designs, based on the elements of a standard cell library are presented in this work: one design involving XNOR and multiplexer gates (XNM), another design utilizing XNOR, AND
High speed low power 8t full adder cell with 45% improvement in threshold loss problem
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Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. Demands for the low power VLSI have been pushing the development of design methodologies aggressively to reduce the power
New design methodologies for high speed low-voltage 1 bit CMOS Full Adder circuits
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New methodologies for 1-Bit XOR-XNOR full adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high speed low-power and low voltage full adder
Low power, high speed full adder architectures in 45nm technology
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I. INTRODUCTION elements because of their extensive use in digital arithmetic and signal processing applications. The importance of a high speed and low power full adder topology is wide felt as the overall performance of a data path design for signal processing for signal
A survey of low power high speed one bit full adder
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In this paper, a structured approach for analyzing the adder design is introduced. Analysis is based on some simulation parameter like No. of transistors, power, delay, power delay product, different technologies, aspect ratio. Each reference used different tool for the
A New High SpeedLow Power 12 Transistor Full Adder Design With GDI Technique
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The low power and high performance 1-bit full adder cell is proposed in this paper. The Gate Diffusion Input (GDI) technique has been used for the simultaneous generation of XOR and XNOR functions. The resulting full adder circuit is realized using of the 12 transistors, while
High Speed and Low Power Basic Digital Logic Gates, Half- Adder and Full Adder Using Modified Gate Diffusion Input Technology
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In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In todays digital world, IC plays a vital role in highperformance computing, communication, and many consumer electronics. IC
Comparative analysis of a low power and high speed hybrid 1-bit full adder for ULSI circuits
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Full adder circuit is a basic building block for designing any arithmetic circuits. Due to high demands and need for low and high speed digital circuits with small silicon area scaling trends have increased tremendously. In this paper a new high speed full adder circuit is
Ultra-low-voltage and high speed 1-bit full adder cell using finfet transistors for mobile applications
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Full Adder is the building block of computing circuits. Designing a Full Adder with the smaller area, low power consumption, and high speed have always been demanded. Since the channel length tends to the nano-scale, the use of MOSFET as a basic device in Full Adder
Delay Optimized Full Adder Design for High Speed VLSI Applications
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The most widely used arithmetic operation in digital applications is addition. Full adder is the most important building block in digital signal processors and controllers as it is used in arithmetic logic circuit (ALU), in the floating point unit and in case of cache or memory
A novel GDI-MUX based low power- high speed 1-bit full adder
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In this work, a novel design for a 1-bit full adder featuring Gate Diffusion Input design technique (GDI) is presented. GDI technique is a power efficient technique for designing digital circuit as compared to most commonly used CMOS techniques. The new full adder is
Performance Analysis of High Speed CMOS Full Adder Circuits For Embedded System
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The full Adder is designed using CMOS logic style by dividing it in three modules so that it can be optimized at various levels. First module is an XOR-XNOR circuit, which generates full swing XOR and XNOR outputs simultaneously and have a good driving capability. The
A high speed 14 Transistor Full Adder Cell using Novel 4 Transistor XOR/XNOR Gates Based on Dynamic CMOS Logic
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This paper presents the novel design of 4T XOR and XNOR gates based on dynamic CMOS logic style. As compared to existing 4T and 6T XOR/XNOR gates, there is no threshold loss problem in the proposed realization. Using the designed gates, full adders (1-bit, 2-bit and 4
Survey on High Speed Low Power Full Adder Circuits
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The performance of an adder has a major effect on the overall performance of a digital system. The adder is the digital circuits which perform addition of the numbers. In many processors and controllers, the adders are used to do the arithmetic and logical operations
Design of Low Power and High Speed Full Adder Cell Using New 3TXNOR Gate
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In the current age of technology advancement it is necessary to design different new concepts to reduce area of the cell as well as power consumption. The adders are always meant to be the most fundamental requirements for process of high performance and other
Study on various GDI Techniques for Low Power, High Speed Full Adder Design
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This paper is an outcome of a survey on different full adders design methodologies using gate diffusion input technique. Gate diffusion input is a technique of low power digital combination design. This technique as compared to other currently used logic design styles
A High Speed Full Adder Circuit using 3 Transistor XOR Gates for Arithmetic Operations of VLSI System
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The necessities to obtain better speed this paper list to a change in parameter of full adder circuit that has been proposed by using 3T XOR gate combining CMOS with pass transistor logic. The design that has been given shows a significant improvement in propagation delay
A NOVEL VLSI ARCHITECTURE OF LOW POWER HIGH SPEED FULL ADDER USING GDI MULTIPLEXER
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In this paper, we propose a new technique for implementing a low power full adder using a set of GDI multiplexers. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have low power operation for the sub
Design of High Speed Low Power Full Adder Using TFET
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ABSTRACT A full adder circuit is considered as one of the fundamental building block for Digital Signal Processors (DSPs), Arithmetic and Logical Units (ALUs), Application Specific Integrated Circuits (ASICs) in VLSI design. So speed power and area are the three main
Design of Low Power High Speed Hybrid Full Adder
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In this paper, a hybrid 1-bit full adder design employing both complementary metal oxide semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using
Analysis of Modified Hybrid Full Adder with High Speed
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In digital CMOS design, power consumption has been a major concern for several years advanced IC fabrication technology allows the use of nano-scale devices so inability to get power to circuits, power leakage or to remove the heat they generate. By optimizing the
Low Power- High Speed 11T Full Adder DSM Design
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Low power designs has become one of the primary focus in Deep Sub-Micron (DSM) Technology. Optimization of speed power and area can be achieved by using Gated Diffusion Input (GDI) technique. In this paper an 11T Adder using GDI technique is proposed
Design of a high speed one-bit full adder circuit
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Full adder circuit is performing an important role in many system applications such digital signal processors, microprocessors, and arithmetic logic units, etc. In this paper, a hybrid high speed one bit full adder is proposed in 130nm technology. The performance
Implementation of Novel Ultra-Low Power and High Speed 1-Bit Full Adder Cell
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This paper presents a novel ultra-low power and high speed 1-bit Full Adder which is designed only based on pass transistor logic. The main advantages of this design are very low propagation delay and ultra-low consumption power, which lead to achieve lower PDP
Design and Implementation of 8-Transistor Full Adder for High Speed Application
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Design and analysis of 8 transistor full adder using 3T XOR gate has been implemented in this paper. The proposed design style has achieved comparatively higher noise margin and speed than the existing structures. Silicon area can be reduced significantly by reducing the
Design and Simulation of High Speed CMOS Full Adder
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Adder are the basic building blocks of any computing system These Arithmetic operations are widely used in most digital computer systems. Addition will be the basic component in arithmetic operation and is the base for arithmetic operations such as multiplication and the
Performance analysis of a low power high speed hybrid 1-bit full adder circuit
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Full adder is one of the most fundamental building block of all the circuit applications. Most full adder systems are considered performance of speed chip area, threshold loss, full swing output, delay and the most important is power consumption. The increasing demand
GROUND BOUNCE NOISE REDUCTION USING HIGH SPEED AND LOW POWER 14T FULL ADDER
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In low power design circuits the leakage power and ground bounce noise are plays a virtual role in the any module. The leakage power consumption and ground bounce noise are effects a performance of the module. In digital electronics adders are used to addition
Design Study of a Low Power High Speed 8 Transistor Based Full Adder Using Multiplexer XOR Gates
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In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the
Design of Low Power High Speed 1-Bit Hybrid Full Adder
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Full adders are the fundamental unit in any digital system. Adders are used for arithmetic calculations so if we improve performance parameters for full adder the speed of arithmetic logic unit can be increased. But main problem with an adder circuit is carry generation and
Performance Analysis of Low Power and High Speed one-bit Full Adder Circuit
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Adders are digital circuits that perform addition of numbers in processors and other kinds of computing devices. This paper presents performance comparison of a one-bit full adder circuit in 130nm technology at a temperature of 27 0C. The circuit is designed and simulated
Design of a Low Power and High Speed 1-bit Hybrid Full Adder
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Adder ) is developed to illustrate the use and application of Hybrid Technology having with focus on Power consumption minimization and high fan-out. In the reference design, while working with constraints of 90nm and 180nm technology, we observed that we achieve an
Low Power Full Adder Cells for Low Voltage and High Speed Applications
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Fundamental building blocks of majority of the arithmetic and logic circuits are produced by XNOR-XOR logic gates. This paper proposes a new 3T (three transistors) XNOR gate and 5T (five transistors) XOR gate with considerable area and power savings. In majority of the
An Alternative Logic Approach to Implement High Speed Low-Power Full Adder Cells
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This paper presents a high speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35 µm CMOS technology and
Comparison of High Speed Low Power Techniques GDI McCMOS in Full Adder Design
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In modern era, VLSI technology has focussed for enhancing the performance, less power requirement and high speed of any digital circuit. Due to scaling style, power dissipation, propagation delay and transistor count (area) need to be concern by VLSI designer as per
A Novel High Speed and Low-Energy 1-Bit Full Adder Cell Based on CNFET Technology
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Using both Capacitive Threshold Logic (CTL) and Transmission Gate Logic (TGL), a novel Full Adder cell based on 32nm Carbon Nanotube Field Effect Transistors (CNFETs) is presented in this paper. This approach leads to decrease both the delay and Power Delay CSE PROJECTS