High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.

Over the past years, silicon-based electronic technology has been improved through downscaling MOSFETs, resulting in higher device performance and density. However, there are still some obstacles to scaling, such as diffusion areas will no longer be separated by a low doped channel region and equivalent gate oxide thickness will fall below the tunnelling limit. Hence, it is important to extend or complement traditional silicon technology. As one of the promising technologies, nanotechnology avoids most of the fundamental limitations for conventional silicon devices. Nanoelectronic is an applicable field of nanotechnology that is producing nanoscale machines and systems efficiently, such as nanowires, nanoparticles and Carbon Nano Tubes (CNT). CNTs have special electronic, thermal and mechanical properties that make them attractive for the future integrated circuit applications. Transistors with carbon nanotubes as their channel are called Carbon Nanotube Field Effect Transistor (CNFET). Recently, some circuit applications are presented based on CNFETs, such as ring oscillators, invertors, and logic gates [1]. Arithmetic operations are extensively used in many VLSI applications such as signal processing, and digital communications [2], [3]. Adders are major part of computational circuits that are used for implementing any other arithmetic operation such as subtraction, multiplication or even logarithmic functions [4],[5]. Hence, efficiency of Adders affects performance of whole system therefore designers attempt to produce more efficient Adders. Many logic styles have been designed since now to produce efficient Full Adder cells. The complementary CMOS and CPL designs are two conventional Adders based on CMOS structure. Based on transmission function and transmission gate, TFA and TGA designs were implemented. The other designs are classified as Hybrid designs. Applying

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