Implementation of a Digital Signal Processor
Implementation of a Digital Signal Processor in a DBF Self-Beam-Steering Array Antenna
FREE-DOWNLOAD T Tanaka, R Miura… – IEICE Transactions on …,
169 rate of 64 kbps can be accommodated assuming a QPSK modulation scheme and four samples
per sym- bol. The resolution of the A/D converters is 8-bit precision. All processing after