Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
FREE-DOWNLOAD X Zhao, DL Lewis, HHS Lee… – … -AIDED DESIGN OF …, 2011 –
30, NO. 5, MAY 2011 Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked
ICs However, pre-bond testability presents unique challenges to 3-D clock tree design. First,
each die needs a complete 2-D clock tree to enable pre-bond test
THREE-DIMENSIONAL system integration has emerged as a key enabling technology to continue the scaling trajectory predicted by Moore’s Law for future integrated circuit (IC) generations. With 3-D integration technology, both the average and maximum distance between components can be substantially reduced by placing them on different dies, which translates into significant savings in delay, power, and area. Moreover, it enables the integration of heterogeneous devices, making the entire system more compact and efficient. Nevertheless, the success of 3-D-stacked ICs is predicated on the final post-bond yield,