Low Power Delay Optimised Buffer Design using 70nm CMOS Technology
FREE-DOWNLOAD D Sharma… – International Journal of Computer …, 2011
slight increase in threshold voltage causes a large amount of leakage power reduction with only
dissipation has been achieved while maintaining same delay as compared to the existing design.
can be used to provide power efficient solutions for portable VLSI applications at
i require some latest research topics on low power
i need some recent research topics
Hi,
recent 2012 research papers for system on chip may be good for you
https://www.engpaper.com/system-on-chip-2012.htm
Guru
send research project full papers on low pwer vlsi
Hi,
low power vlsi research papers
https://www.engpaper.com/free-research-papers-and-projects-on-low-power-vlsi.htm
Guru