Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
FREE-DOWNLOAD R Wang, NC Chou, B Salefski… – … Conference, 2009. DAC’ …, 2009 –
ABSTRACT Power consumption of system-level on-chip communications is becoming more
significant in the overall system-on-chip (SoC) power as technology scales down. In this
paper, we propose a low power design technique of gated bus which can greatly reduce