ENGINEERING RESEARCH PAPERS

system on chip SOC vlsi research papers recent 2014




CyberPhysical-System-On-Chip (CPSoC): A Self-Aware MPSoC Paradigm with Cross-Layer Virtual Sensing and Actuation
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Abstract:Cyberphysical systems (CPSs) are physical and engineered systems whose operations are monitored, coordinated, controlled, and integrated by a computing, control, and communication core. We propose Cyberphysical-System-on-Chip (CPSoC), a new
Day to day computing has moved from mainframe to personal to ubiquitous computing over the last several decades [1]. Ubiquitous computing is almost imperceptible and yet is everywhere around us, enabled by the proliferation of embedded systems. An embedded

Performance Optimization for System-on-chip Using Network-on-Chip and Data Compression
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Abstract:The growing complexity in consumer embedded products has led to new tendencies that forecast heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-

Optimizing System-On-Chip verifications with multi-objective genetic evolutionary algorithms
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ABSTRACT. Verification of semiconductor chip designs is commonly driven by single goal orientated measures. With increasing design complexities, this approach is no longer effective. We enhance the effectiveness of coverage driven design verifications by

System on Chip Based Embedded Products
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ABSTRACT This study proposes a method of high speed data transfer by Advanced Microprocessor Bus Architecture (AMBA) based Direct Memory Access (DMA) controller using asynchronous first in first out (FIFO). Direct Memory Access Controller (DMAC) is
The increasing demand of applications in consumer electronics has increased the number of computing resources in single-chip. The traditional communication architecture in SoC is not capable to address the increasing bandwidth requirements of future large systems.

Design and Implementation of a Face Recognition System-on-a-Chip for Wearable/Mobile Applications
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ABSTRACT This paper describes the design and implementation of a System-on-a-Chip (SoC) for face recognition to use in wearable/mobile products. The design flow starts from the system specification to implementation process on silicon. The entire process is

Optimization of logic area for System on Programmable Chip based on hardware-software partitioning
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Abstract:T In this paper, we propose an approach based on hardware-software partitioning to minimize logic area of a SOPC circuit" System on a Programmable Chip". This approach minimizes the SOPC area while satisfying a time constraint. To minimize this area, we

Object-Oriented System-on-Network-on-Chip Template and Implementation
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Abstract Network-on-chip (NoC) technology enables a new system-onchip paradigm, the system-on network-on-chip (SoNoC) paradigm. One of the challenges in designing applicationspecific networks is modeling the on-chip system behavior and determining on-

System-level Modeling of a Lab-On-Chip for Micropollutants Detection
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Abstract:The issue addressed by this paper is system-level modeling of Lab-On-Chip (LOC) level. These microsystems integrate within a single chip many functions from several domains such as electronics, thermic, biochemistry or microfluidics. The modeling of these

Development of intelligent traffic control system based on FPGA and single chipmicrocomputer technology.
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ABSTRACT There are a large number of combinatorial logic resources in FPGA, can complete the design of combinational logic circuit, larger scale. Microcontroller design of intelligent traffic light control system, change of state control signal by SCM, basically can

Reliability Design of Ship Main Engine Remote Control System Based on Single ChipMicrocomputer
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According to the development direction of ship engine, this paper talks about the reliability design of ship main engine remote control system based on single chip microcomputer, including the system design of microcontroller, software and hardware reliability. Also, it

Wheeled Mobile Robot Based on 51 Single Chip Computer Control System Design
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Research and Development of Agricultural Machinery Operating Area Measuring System Based onSingle Chip Computer
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Mechanical products is widely used in agriculture now, but lacks a kind of operating area measuring system. Therefore, a kind of Intelligent operating area measuring system, simple

Based on Single Chip Microcomputer and C# Carving Machine Control System Design
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Architecture of Multi-Core System-on-the-Chip with Data Flow Computation Control
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Abstract:System-on-the-chip can be defined as the integrated circuit (chip) which integrates all necessary components of the computer or other system. This paper deals with the architecture of multi-core system-on-the-chip that is based on the data flow paradigm

LOW-POWER HEALTH-MONITORING INSTRUMENTATION BASED ON A PROGRAMMABLE SYSTEM-ON-CHIP
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In recent years, the world is being competitive, and to be in the race of tension and this leads to many health problems specially heart related problems. In recent days, wireless sensor networks are used to structure home-care system in many researches. Wireless sensor

Low Latency on Chip Permutation Network for Multiprocessor System On-Chip
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Abstract: This On-Chip Permutation Network for Multiprocessor System-On-Chip presents the silicon-proven design of a novel on-chip network to support guaranteed traffic permutation in multiprocessor system-on-chip applications the routing algorithm, the

VHDL implementation of Flight Control functions of Quadcopter and its integration in Zynq SoC (System on Chip)
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Abstract Unmanned Aerial Vehicles (UAVs) are widely used in both industry and academic area. The Flight Control (FC) is the key function which allows stable flight in the air. Typically it is implemented in software using small microcontrollers. In order to do Mission based

SOC old papers research papers



System-on-Chip
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For the next decade, Moore's Law is still going to bring higher transistor densities allowing Billions of transistors to be integrated on a single chip. However, it became more and more obvious that exploiting significant amounts of instructionlevel parallelism with deeper
APRIL–JUNE 1999 49 ification and test, and layout and geometrical design of SOCs. However, with technologies such as chip-scale packaging, ball grid array, and direct chip attachment promising silicon efficiencies of 80% in the next few years, SOPs may be more

A 0. 18 µm CMOS 10–6 lux bioluminescence detection system-on-chip
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Chip Characteristics 0.18 µm CMOS (CIS) process 5mm x 5mm (492K transistors) 8 x 16 pixel array (230µm sq.) P+/N/Psub photodiode Pseudo-differential pixel Per-pixel 2-step 13-bit ADC Integrated ramp generator Per-column DSP 320 Mbits/s readout rate Static

SYSTEM-ON-CHIP
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The number of consumer electronics devices sold worldwide is growing rapidly. A total of 2.1 billion consumer electronics devices with a total value of $1.3 trillion were sold worldwide in 2006. It is expected that by 2010 this has grown to over 3 billion devices with a total value

System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design
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The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications
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Semiconductor technology is now approaching 100 nanometer feature size and will soon be below 100 nanometer. This technology trend presents new challenges in analog-digital mixed signal circuit design. A mixed signal circuit must be integrated on a single chip

System level design of reconfigurable systems-on-chip
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Abstract Asynchronous circuits can provide an elegant and high performance interconnect solution for synchronous systemon-chip (SoC) designs with multiple clock domains. This globally asynchronous, locally synchronous(GALS) approach simplies global timing

Digital camera system on a chip
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ABSTRACT Since the early 1990s, there has been an explosion of activity in the area of CMOS image sensors. Up until recently, the dominant and nearly only solid-state image sensor technology was the charge-coupled device (CCD). However, most
Abstract This work presents an architectural solution for the IEEE 802.11 a MAC layer on- chip implementation. The complete implementation flow is presented as well as some unique solutions implemented using an architecture that exploits dedicated hardware for

VFAT2: A front-end system on chip providing fast trigger information, digitized data storage and formatting for the charge sensitive readout of multi-channel
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Abstract The architecture, key design parameters and results for a highly integrated front- end readout system fabricated as a single ASIC are presented. The chip (VFAT2) comprises complex analog and digital functions traditionally designed as separate components.

A dynamic memory management unit for embedded real-time system-on-a-chip
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ABSTRACT Dealing with global on-chip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for upcoming billion transistor multiprocessor System- on-a-Chip (SoC) designs. To achieve this, we propose a new memory management

Atalanta: A new multiprocessor RTOS kernel for system-on-a-chip applications
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Abstract This paper introduces a new multiprocessor real-time operating system (RTOS) kernel that is designed as a software platform for System-On-Chip (SoC) applications and hardware/software codesign research purposes. This multiprocessor RTOS kernel has the

Non-destructive on-chip cell sorting system with real-time microscopic image processing
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Abstract Studying cell functions for cellomics studies often requires the use of purified individual cells from mixtures of various kinds of cells. We have developed a new non- destructive on-chip cell sorting system for single cell based cultivation, by exploiting the ABSTRACT IBM's experience with core based designs and the methodology support required for system on a chip (SOC) designs is discussed. An overview of the different styles of SOC designs used in the industry today, the tradeoffs made when cores were designed,

A TIQ based CMOS flash A/D converter for system-on-chip applications
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Abstract The analog-to-digital converter (ADC) is an essential part of system-on-chip (SoC) products because it bridges the gap between the analog physical world and the digital logical world. In the digital domain, low power and low voltage requirements are

System-on-a-chip cosimulation and compilation
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Background Figure 1 shows the videophone system's main operators, which communicate through a set of buses. To meet performance requirements, company designers used fully hardwired blocks for some of these operators (for example, the motion estimator2). But to

Switched interconnect for system-on-a-chip designs
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Abstract With the increased use of IP cores in chip designs, an increasing amount of time is spent on design and verification of glue logic. To solve this problem together with the bottleneck problem of arbitration based buses, a novel approach in system-on-a-chip

System-on-Chip Designs
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Conventionally, ASIC design involved development of medium complexity Integrated Circuits (of less than 500,000 gates). These had a cycle time of roughly 6 months, were processed with 0.35 u technology, and were essentially made up of core logic and some

Parallel modelling paradigm in multimedia applications: Mapping and scheduling onto a multi-processor system-on-chip platform
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Abstract Multi-processor systems have appeared as a promising alternative to face the difficulties of creating even faster uni-processor systems using latest technologies. Emerging design paradigms such as Multiprocessor System-ona-Chip (MpSoC) offer high levels of

A test access control and test integration system for system-on-chip
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Page 1. A Test Access Control and Test Integration System for System-on-Chip Chih-Wea Wang, Jing-Reng Huang, Kuo-Liang Cheng, Huan-Sheng Hsu, Chih-Tsun Huang, Cheng-Wen Wu, and Youn-Long Lin Page 2. Outline Introduction

The Hyperprocessor: A template System-on-Chip architecture for embedded multimedia applications
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ABSTRACT We describe and evaluate a template architecture for SoC systems intended for multimedia applications. The architecture is a 2-level hierarchy that consists at the bottom level of several processing units (PUs), controlled at the top level by a control processor.

Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs.
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The realization of space-efficient support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. Novel approaches to designing aliasing-free space compaction hardware were recently proposed in the context of testing

SOAP based distributed simulation environment for System-on-Chip (SoC) design
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Abstract In this paper we present a distributed simulation environment for System-on-Chip (SoC) design. Our approach enables automatic generation of, geographically distributed, SystemC simulation models for IP-based SoC design and eases communication between

System-on-chip test parallelization under power constraints
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This paper deals with test parallelization (scan-chain subdivision) which is used as a technique to reduce test application time for systems-on-chip. An approach for test parallelization taking into account test conflicts and test power limitations is described. The

4G MC-CDMA multi antenna system on chip for radio enhancements (4MORE)
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ABSTRACT The IST project 4MORE will research and develop an innovative architecture suitable for the advanced signal processing techniques involved in MC-CDMA and employing multiple antennas.target in terms of broadband capabilities, the

Microelectronic System-on-Chip modeling using objects and their relationships
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Abstract System-on-chip design introduced many new challenges for engineers. Among them, complexity management and reuse are important issues. Many efforts address complexity by raising the level of abstraction to increasingly functional levels. However, at

A Low Complex Scheduling Algorithm for Multi-processor System-on-Chip.
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Abstract Multi-Processor System-on-Chip (MPSoC) represents today the main trend for future architectural designs. Nonetheless, the scheduling of tasks on these distributed systems is a major problem since it has a central impact on global performances. This

A generic system simulator with novel on-chip cache and throughput models for gigascale integration
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The historically unmatched progression of integrated circuit technology over the last thirty- five years has enabled many generations of increased computing performance and functionality. Future opportunities for microelectronics technology are governed by a

Interconnect IP for gigascale system-on-chip
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Abstract–Today's electronic systems merge multimedia, data and signal processing, and digital communication functions on single die. Thus these systems are becoming true SoC (System-on-Chip) designs. This development is making traditional design and

System on a Chip: Changing IC design today and in the future
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The semiconductor industry, although more than 50 years old, continues to rapidly change in numerous ways. Cus- tomers, or set makers, have become global players. They are moving design and manu- facturing to places where it can be done most effectively or where resources

System-level simulations investigating the system-on-chip implementation of 60-GHz transceivers for wireless uncompressed HD video communications
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In 2001, the Federal Communications Commission (FCC) allocated an unlicensed 7-GHz wide band in the radio-frequency (RF) spectrum from 57 to 64 GHz for wireless communications (FCC, 2001). This is the widest portion of radio-frequency spectrum ever

Designing a simple fpga-optimized risc cpu and system-on-a-chip
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Abstract–This paper presents the complete design of a simple FPGA RISC processor core and system-on-a-chip in synthesizable Verilog. It defines a RISC instruction set architecture and then describes how to implement every part of the processor. Next, an interrupt facility

Embedded Software Design and Programming of Multiprocessor System-on-Chip
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Abstract This chapter introduces the definitions of the basic concepts used in the book. The chapter details the software and hardware organization for the heterogeneous MPSoC architectures and summarizes the main steps in programming MPSoC. The software

System-on-chip design methodology in engineering education
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Abstract: The system-on-chip design methodology is a new paradigm for electrical and computer engineering education in digital logic and microelectronics. The development of a close relationship between the undergraduate course sequence in digital logic and

System-on-chip testability using LSSD scan structures
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IBM Microelectronics large test area reduction. Embedded memories, cores, and chips on multichip modules and boards can also benefit from such unified, flexible DFT methodology, which allows testing of the entire system with a single test protocol. The LSSD boundary

On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in System-on-Chip Devices.
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ABSTRACT On-chip Built-In Self-Test (BIST) based diagnosis of the embedded Field Programmable Gate Array (FPGA) core in a generic System-on-Chip (SoC) is presented. In this approach, the embedded processor core in the SoC is used for reconfiguration of the

FIPSOC: A field programmable system on a chip
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Abstract In this paper we present a novel RAM-based field programmable mixedsignal integrated device consisting of a Field Programmable Gate Array (FPGA), a set of programmable and interconnectable analog cells, and a microprocessor core. This

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