ENGINEERING RESEARCH PAPERS

VLSI IEEE PAPER 2018




A Review Paper on Multiplier Algorithms for VLSI Technology
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ABSTRACT In the era of digitalization, it is required to increase the speed of digital circuits while reducing area and power consumption. In any digital system, multiplication is a key element. One of the important parameter which affects the performance of entire system is

Low Cost VLSI Architecture for Proposed Adiabatic Offset Encoder and Decoder
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ABSTRACT A network-on-chip (NoC) improves the technology and the power dissipated starts to opposed with by the additional elements of the correspond ion subsystem. Sample adaptive encoder architecture has been acquired as a new in-loop filtering block. To get the

VLSI CIRCUIT OPTIMIZATION FOR 8051 MCU
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ABSTRACT With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5- m process technology. Hence

Analysis of Optimization Techniques for Low Power VLSI Design
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ABSTRACT With shrinking technology, as power density (measured in watts per square millimetre) is raising at an alarming rate, power management is becoming an important aspect for almost every category of design and application. Reducing power consumption

SDR Applications using VLSI Design of Reconfigurable Devices
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ABSTRACT The design of future multi-standard systems is very challenging. Flexible architectures exploiting processing commonalities of the different set of standards cohabiting in the device offer promising solutions. This paper presents a graphical approach for the

High Speed VLSI Architecture for Squaring Binary Numbers Using Yavadunam Sutra and Bit Reduction Technique
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ABSTRACT The boom of high speed recent communication hardly requires the efficient Mathematical operations. The favored performance outcomes of any architecture are possible only by the effective Mathematical operations. Squaring plays an essential role in

Design of Improved Distributed Canny Edge Detection Algorithm (IDCEDA) and its VLSI Implementations
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ABSTRACT Recently Automatic Image Segmentation and edge detection techniques have become more popular and commonly used in many applications like Road Sign Detection in ADAS systems, Medical Image Diagnosis Machine vision systems etc. Generally

A Low Power VLSI Implementation of Reconfigurable FIR Filter Using Carry Bypass Adder
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ABSTRACT : Reconfigurable Finite Impulse Response (RFIR) filter plays an important role in Software Defined Ratio (SDR) systems, whose filter co-efficient change dynamically during runtime. In this paper, Low Cost Carry Bypass adder Reconfigurable Finite Impulse

Enhanced VLSI Architecture of Partial Product Generator using Redundant Binary Modified Partial Product Generator Method
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ABSTRACT Adders are the key component of the arithmetic unit, particularly quick parallel addition. Redundant Binary Signed Digit (RBSD) adders are intended to perform high-speed arithmetic operations. For the most part, in a high radix adjusted Booth encoding calculation

A Greedy Iterative Algorithm and VLSI Implementation Strategy for Multiuser Detection
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ABSTRACT Multiuser detection (MUD) strategies have the poten-tial to significantly increase the capacity of wireless communications systems, but for these to be useful they must also be practical for implementation in VLSI circuits that cope with real world situations and

Comprehensive Evaluation of Crosstalk and Delay Profiles in VLSI Interconnect Structures with Partially Coupled Lines
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ABSTRACT : In this paper, we present a methodology to explore and evaluate the crosstalk noise and the profile of its variations, and the delay of interconnects through investigation of two groups of interconnect structures in nano scale VLSI circuits. The interconnect structures
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