vlsi system on chip
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vlsi system on chip


Test wrapper and test access mechanism co-optimization for system-on-chip
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V Iyengar, K Chakrabarty ,Journal of Electronic Testing, 2002 ,Springer
 Manufactured in The Netherlands. Test Wrapper and Test Access Mechanism Co-Optimization
for System-on-Chip *  Editor: C. Landrault Abstract. Test access mechanisms (TAMs) and test
wrappers are integral parts of a system-on-chip (SOC) test architecture. 

The torus routing chip
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WJ Dally ,Distributed computing, 1986 ,Springer
 The TRC is a self-timed VLSI circuit that pro- vides deadlock-free packet communications in k-
ary n-cube (torus) networks [12] with up to k = 256 Page 2.  4 System design The torus routing
chip (TRC) can be used to con- struct arbitrary k-ary n-cube interconnection net- works. 

Future-ready Ultrafast 8bit CMOS ADC for system-on-chip applications
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J Yoo, D Lee, K Choi ,Power, 2001 ,cse.psu.edu
 REFERENCES [1] J. Yoo, K. Choi, and A. Tangei. A 1-GSPSCMOS Flash A/D Converter
for System-on-Chip Applications. IEEE Com- puter Society Workshop on VLSI, pp.

PIXEL {PLANES: Building a VLSI {based graphic system
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J Poulton, H Fuchs, JD Austin, JG Eyles , Hill conference on VLSI, 1985 ,cs.unc.edu
 3. System Realiaationa This section describes our experiences building several Pixel- planes
display systems. Our first enhanced memory chip was in- tended as a first VLSI design
exercise and not intended to be- come part of a working display. 

A system-on-chip design methodology emphasizing dynamic memory management
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D Verkest, JL Da Silva, C Ykman, K Croes ,The Journal of VLSI , 1999 ,Springer
MATISSE is a design environment intended for developing systems characterized by a tight
interaction between control and data-flow behavior, intensive data storage and transfer, and
stringent real-time requirements. Matisse bridges the gap from a system specification, 

Will networks on chip close the productivity gap?
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A Jantsch ,Networks on chip, 2004 ,Springer
 Addressing the system-on-a-chip interconnect woes through communication-based design.  A
network on chip architecture and design methodology. In Proceedings of IEEE Computer Society
Annual Symposium on VLSI, April 2002. William J. Dally and Brian Towles. 

A robust analog VLSI motion sensor based on the visual system of the fly
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RR Harrison ,Autonomous Robots, 1999 ,Springer
 The CPU system consumed an addi- tional 24%, and much of the CPU’s time was 
Biologically-inspired analog VLSI approaches to this problem can bring down the cost and make
robot  motion sensor that includes photoreceptors and motion pro- cessing on the same chip is 

HIBI communication network for system-on-chip
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E Salminen, T Kangas, TD Hämäläinen ,The Journal of VLSI , 2006 ,Springer
Abstract This paper presents a communication network targeted for complex system-on-chip
(SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection
(HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with 

A 3D-DCT real-time video compression system for low complexity single-chip VLSIimplementation
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A Burg, R Keller, J Wassner, N Felber ,Proceedings of the , 2000 ,iis.ee.ethz.ch
Abstract: This paper presents the first VLSI implementation of a real-time color video
compression/decompression system, based on the threedimensional discrete cosine
transform (3D-DCT). Compared to motion-estimation/compensation based algorithms, the 


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