Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements-free research papers, vlsi
FREE-DOWNLOAD J Narasimham, K Nakajima, CS Rim… – … -Aided Design of …,
Abstract- In an approach recently proposed for the yield enhancement of programmable gate
arrays (PGA’s), an initial placement of a circuit is first obtained using a standard technique such
as simulated annealing on a defect-free PGA. In the next step, this placement is .
Receiver ASIC for timing, trigger and control distribution in LHC experiments
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