65nm CMOS DAC


A 12 bit 2.9 GS/s DAC With IM360 dBc Beyond 1 GHz in 65 nm CMOS

FREE-DOWNLOAD [PDF] from tue.nlCH Lin, FMI van der Goes, JR Westra… – Solid-State Circuits

A floating-gate trimmable high-resolution DAC in standard 0.25 µm CMOS
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We have built a 14-bit digital-to-analog converter ( DAC ) in a standard 0.25 µm digital CMOS process. We use analog values stored on floating-gate p-channel MOSFETs to trim the DAC linearity. Because the storage is nonvolatile, we eliminate the need for continuous trimming

Design of Low Power 10GS/s 6-Bit DAC using CMOS Technology
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A Low power 6-bit R-2R ladder Digital to Analog Converter is presented in this paper. Here the R-2 R network designed using resistors with only two values-R and 2xRand the switch is designed by using both NMOS and PMOS Transistors. This Digital to Analog Converters

Design Strategy of Current Source in Current-Steering CMOS DAC
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ABSTRACT A new design strategy of current sources in CMOS current-steering segmented digital-to-analog converter ( DAC ) used into a RF transmitter stage for 2.45 GHz Bluetooth applications, is presented. The design strategy is based on an iterative scheme whichAfter the definitions, we will focus on DACs first. The main limitations in DACs are a result of mismatch, either between transistors or between passives as resistors and capacitors. The AD Converters will be discussed. The principles of the more important types will be

A 6-bit, 0.1-V DAC Based on an M-2M Ladder Network in IBM 130 nm CMOS
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This paper presents the design of an ultralowvoltage DAC using a transistor-only R-2R ladder network in the IBM 130 nm CMOS technology. The building blocks of the converter are firstly described, which include a binary current division circuit and an amplifier both

CMOS 8-bit binary type current-steering DAC
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ABSTRACT A CMOS 8-bit binary type current steering Digital to Analog Converter DAC with dynamic random return to zero technique to improve dynamic performance is presented in this paper. Current steering DAC has advantage of constant output impedance and high

AD7528Dual 8-Bit CMOS DAC Application Note
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ENTRODUCTION The AD7528 is a monolithic dual 8-bit CMOS DAC packaged in a 20-pin DIP. Each DAC has its own 8-bit data latch which loads data from a common 8-bit data bus (see Figure 1). Since both DACs are fabricated on the same chip, precise matching and

Design of 16 bit 180nm CMOS Fully Segmented DAC
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Due to increasing advancement in technology in the field of digital signal processing, data converters such as analog to digital converters and digital to analog converters with high resolution are profoundly required but problem with incorporating these data converters

A VERSATILE CMOS DAC -DR1VER FOR RESIS ACTUATORS
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SUMMARY A system for the digita! signal processing and the direct driving of a resistive actuator is described. The digital section uses oversampling and linear interpolation techniques to obtain a significant chip area reduction without degrading conversion

A 10-bit 160-MSPS 2.5-V Segmented Current Steering CMOS DAC for WLAN Applications
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MC Chen, CC Liu, CC Tien 140.117.166.1 This paper presents a 10-bit 160-MSPS 2.5-V digital to analog converter ( DAC ) and is implemented in TSMC 0.25 µm CMOS technology. A segmented current steering architecture is used with optimized performance for speed, resolution, power consumption

10-Bit Current Steering DAC in CMOS 130nm Technology
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This paper proposed a 10-bit current steering (segmented architecture) digital-to-analog converter, with different sizes of current sources. The proposed 10-bit digitalto-analog converter was implemented using TSMC CMOS 130 nm 1P2M technology. The power

A 130-NM CMOS 400 MHZ 8-BIT LOW POWER BINARY WEIGHTED CURRENT STEERING DAC
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ABSTRACT A low power low voltage 8-bit Digital to Analog Converter consisting of different current sources in binary weighted array architecture is designed. The weights of current sources are depending on the binary weights of the bits. This current steering DAC is

Design of 12-Bit DAC Using CMOS Technology
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Digital-to-Analog Converter ( DAC ) is used to convert a digital form of input into an analog form of output. In this paper, a digital-to-analog converter which is based on the R-2R ladder is analyzed for low power consumption ie 27.04 mW, low active chip area ie. 054 mm2 and

Design and Analysis of CMOS Thermometer Current Steering DAC to Remove Non-Linearity
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ABSTRACT The Current Steering Data Converter with Thermometer technique is designed and analyzed utilizing 180nm technology in Cadence Virtuoso Simulation tool along with power supply of 1.8 V. Implementation of DAC is accomplished in such a manner that the

A 2 GS/s, 6-bit DAC for UWB applications in 0.18 μm CMOS technology
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To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra

CMOS , 330 MHz Triple 8-Bit High Speed Video DAC
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A 12-bit 220-MS/s Area-efficient DAC in 65 nm CMOS with Calibration- DAC Assisted Linearity Enhancement
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DAC in 65 nm CMOS with a 3rd-order harmonic canceling calibration DAC is presented. The calibration DAC removes cubic error caused by finite output impedance by injecting correction current corresponding to the opposite of the INL error. To more effectively enable

A Power Efficient, High Gain R-2R Ladder DAC Designed in 90nm CMOS Technology
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In modern wireless communication system there is a need of broad band transmission of image, audio or video at high data rate, requiring high speed data converters for transmission. In this work an 8 bit Digital to Analog Converter ( DAC ) is designed, simulated

POWER CONSUMPTION OPTIMIZATION OF 8 BIT, 2 MHz VOLTAGE SCALING SUBRANGING CMOS 0.5-цт DAC
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We present the design of an 8-bit voltage-scaling, subranging Digital-to-Analog converter with a current-biased floating fine ladder. The basic structure has been analyzed and optimized for the best trade-off between conversion speed and power dissipation. This

A 350-MS/s Continuous-Time Delta Sigma Modulator With a Digitally Assisted Binary- DAC and a 5-Bits Two-Step-ADC Quantize in 130-nm CMOS
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Two techniques to improve the performance of continuous-time delta sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) without dynamic element matching