A model driven engineering design flow to generate VHDL
A model driven engineering design flow to generate VHDL-download
The ModEasy project seeks to develop techniques and software tools to aid in the development
of reliable microprocessor based electronic (embedded) systems using advanced development
and verification systems. The tools are evaluated in domains such as the automotive
COMMENT vlsi
A VHDL implementation of an on-board ACF application targeting FPGAs
Static Analysis of VHDL Model Evaluation
FREE IEEE PAPER