An Efficient Algorithm to Selectively Gate Scan Cells for Capture Power Reduction
FREE-DOWNLOADJC Rau, CL Wu… – Tamkang Journal of Science and Engineering, 2011 –
Full scan testing, one of the DFT (design-for-testability) technique, is a strategy based on full-scan design by changing all the storage elements into scan cells and stitch them together to form to single or multiple scan chains. In a full-scan design circuit, there are two operation modes during scan testing, shift mode and capture mode, respectively. In shift mode, the test vectors can be shifted into the circuit under test (CUT) in serial through the scan chain. In capture mode, the test responses are captured into each scan cell hence shifted out at the next shift cycle. Fault coverage, test application time, area overhead, etc, were the main factors for test engineers previously . However, as the coming of high clock frequency and deep sub micron (DSM) technology, power saving is a critical objective, if not so, excessive power dissipation can bring the risk of chip to overheating or damaging, even unstable behaviour or manufacturing yield loss due to the occurrence of power peaks. As a result, power dissipation can not be ignored in test development. To achieve power reduction, ad hoc solutions for industrial were practiced early. The first solution is to reduce the test clock frequency. The second solution is to divide the system-under-test (SUT), or to scheme out an adoptable test schedule. The third solution is to oversize the power supply, or cooling device, break points are even added during test application. The first solution cost less hardware than the second and the third solutions, but is difficult to detect the dynamic faults due to the reduced frequency. Although the second solution can detect dynamic faults, the cost of hardware is increased, such as the third solution. Test application time is also lengthened due to these three solutions.