An interface methodology for retargettable fpga peripherals
FREE-DOWNLOAD TL Lee… – Engineering of Reconfigurable …, 2011
Initially, IP cores in System-On-Chip (SOC) were interconnected through custom interface
logics. The more recent use of standard on-chip buses has eased integration and eliminated
inefficient glue logic, and hence boosted the production of IP functional cores.
Using Hard Macros to Reduce FPGA Compilation Time
FPGA-based set-up for RF power amplifier dynamic Supply with real-time digital adaptive predistortion
FREE IEEE PAPER