Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
FREE-DOWNLOAD MD Ker, CY Wu, T Cheng… – Very Large Scale …,
Capacitor-couple technique used to lower snapback- trigger voltage and to ensure uniform
ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is
proposed. The coupling capacitor is realized by a poly layer right under the wire-bonding
IEEE-PAPER
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC IEEE PAPER
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