Design Methodologies and Architectures for Digital Signal Processing on FPGAs

FREE-DOWNLOAD S Mirzaei – 2010
There has been a tremendous growth for the past few years in the field of embedded systems, especially in the consumer electronics segment. The increasing trend towards high performance and low power systems has forced researchers to come up with innovative design methodologies and architectures that can achieve these objectives and meet the stringent system requirements. Many of these systems perform some kind of streaming data processing that requires the extensive arithmetic calculations.  FPGAs are being increasingly used for a variety of  computationally intensive applications, especially in the realm of digital signal processing (DSP). Due to rapid increases in fabrication technology, the current generation of FPGAs contains a large number of configurable logic blocks (CLBs) and several other features such as onchip memory, DSP blocks, clock synthesizers, etc. to support implementing a wide range of arithmetic applications. The high non-recurring engineering (NRE) costs and long development time for application specific integrated circuits (ASICs) make FPGAs attractive for application specific DSP solutions.Even though the current generation of FPGAs offers  variety of resources such as logic blocks, embedded memories or DSP blocks, there is still limitation on the number of these resources being offered on each device. On the other hand, a mixed DSP/FPGA design flow introduces several challenges  to the designers due to the integration of the design tools and complexity of the algorithms. Therefore, any attempt to simplify the design flow and optimize the processes for either area or performance is appreciated.  This thesis develops innovative architectures and methodologies to exploit FPGA resources effectively. Specifically, it introduces an efficient method of implementing FIR filters on FPGAs that can be used as basic building blocks to make various types of DSP filters. Secondly, it introduces a novel implementation of correlation function (using embedded memory) that is vastly used in image processing applications. Furthermore, it introduces an optimal data placement algorithm for power consumption reduction on FPGA embedded memory blocks. These techniques are more efficient in terms of power consumption, performance and FPGA area and they are incorporated into a number of signal processing applications. A few real life case studies are also provided where the above techniques are applied and significant performance is achieved over software based algorithms.  The results of such implementations are also compared with competing methods and trade-offs are discussed. Finally, the challenges and suggestions  of integrating such methods of optimizations into FPGA design tools are discussed.