Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit
FREE-DOWNLOAD P Shanmugasundaram… – VLSI Test Symposium, 2011 –
a commonly used method for testing digital VLSI circuits,
spends a large Reduction of test application time in power-constrained testing by
We dynamically monitor per cycle scan activity to speed up the scan clock for low activity cycles without exceeding the speciﬁed peak power budget. The activity monitor is implemented either as on-chip hardware or through presimulated and stored test data. In either case a handshake protocol controls the rate of test data ﬂow between the automatic test equipment (ATE) and device under test (DUT). The test time reduction accomplished depends upon an average activity factor For low, about 50% test time reduction is analytically shown. With moderate activity, simulated test data gives about 25% test time reduction for ITC02 benchmarks. For full scan s38584, the dynamic scan clock control reduced the test time by 19% when fully speciﬁed ATPG vectors were used and by 43% for vectors with don’t cares. BIST with dynamic clock showed about 19% test time reduction for the largest ISCAS89 circuits in which the hardware activity monitor and scan clock control required about 2-3% hardware overhead.