# Energy efﬁcient asymmetric binary search switching technique for SAR ADC

An asymmetric binary search switching technique for a successive approximation register (SAR) ADC is presented, and trade-off between switching energy and conversion cycles is discussed. Without using any additional switches, the proposed technique consumes 46% less switching energy, for a small input swing (0.5 Vref P-P), as compared to the last reported efﬁcient switching technique in literature for an 8-bit SAR ADC. For a full input swing (2 Vref P-P), the proposed technique consumes 16.5% less switching energy. Introduction: Owing to its low energy consumption, successive approximation register (SAR) ADCs are preferred for wireless and biomedical applications [1]. Of the three major building blocks of a SAR, the energy consumption of digital and comparator logic scales down with technology, but it is not the case with the capacitive DAC (including reference buffer). Energy consumption in the capacitive DAC depends on the total capacitance, input signal swing, and the switching technique used. For a given signal swing, noise and linearity requirements are the key factors which dictate the total capacitance. Switching technique, however, can play an important role in deciding energy consumption. By modifying the way capacitors are switched, switching energy can be reduced. Some of the recently proposed efﬁ- cient switching schemes include Vcm-based switching [2] and monotonic switching [3]. In this Letter, we propose an energy efﬁcient switching scheme based on an asymmetric binary search algorithm. The proposed scheme achieves switching energy efﬁciency by exploiting the switching energy and conversion cycle trade-off. Asymmetric binary search switching technique: In a conventional binary search, for a positive input signal, after the sign comparison, the MSB capacitor is connected to Vref If the input is less than 1/2Vref .

,

then either the complete or a part of the MSB capacitor is discharged

by connecting it to ground. This discharge operation (down transition

[4]) is the main cause of switching energy inefﬁciency in the conventional binary algorithm. Among various switching algorithms, linear

search switching is the most switching-energy-efﬁcient search algorithm, as shown in Fig. 1b, where one unit capacitor is connected to

Vref

at a time. Linear search achieves its switching energy efﬁciency

by ensuring that no capacitor is unnecessarily charged during the

search operation. However, additional comparison operations equate to

energy consumption in the comparator and digital logic. Moreover, for

an n-bit SAR, linearly switching a unit capacitor at a time requires 2

switches in a conventional algorithm, and

their corresponding drivers, which add to layout and digital logic complexity. Thus, the linear switching algorithm represents one extreme of

the trade-off between saving in switching energy and energy dissipated

during additional comparison cycles. Without using any additional

switches, the proposed asymmetric search algorithm exploits this tradeoff to save switching energy by slightly increasing the comparison cycles

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