fpga-field programmable gate arrays-research papers-2012 section 11





 High Fidelity Hybrid Hardware-in-the-Loop Simulator with FPGA and Processor for AC Railway Traction
free download

IJ Böcker, M Sun, ZCPDL Tong, H Zou, P Ranjan ,ee.iitb.ac.in
Abstract In this paper, a high fidelity hybrid real time hardware-in-the-loop (HiL) simulator
using FPGA and real time processor is introduced and its application on an AC railway
vehicle traction system composed of power electronic converter and induction motor is 

 Electronic-and Mobile-Learning in Electronics Courses Focused on FPGA
free download

GV Persiano, S Rapuano ,cdn.intechopen.com
Distance learning is the practical and cost-effective solution to deliver education and training
in places where University classes and professional courses are not offered due to lack of
local expertise or low student enrolment. Its potentiality was recognized since Internet 

 An FPGA realization of simplified turbo decoder architecture
free download

S Verma, S Kumar
The key issue of applying Turbo codes is to find an efficient implementation of turbo
decoder. This paper addresses the implementation of a simplified and efficient turbo
decoder in field programmable gate array (FPGA) technology. A simplified and efficient 

 Hardware Development of Baseband Transceiver and FPGA-Based Testbed in 8× 8 and 2× 2 MIMO-OFDM Systems
free download

S Yoshizawa, Y Miyanaga ,ecti-thailand.org
ABSTRACT Multiple-input multiple-output orthogonal frequency multiplexing (MIMO-OFDM)
is powerful in enhancing communication capacity or reliance. The IEEE802. 11n standard
defines use of four spatial streams in spatial division multiplexing (SDM). The task group 

 DESIGN ENHANCEMENT OF COMBINATIONAL NEURAL NETWORKS USING HDL BASED FPGAFRAMEWORK FOR PATTERN RECOGNITION
free download

J FAN ,eng.fiu.edu
ABSTRACT The fast emerging highly-integrated multimedia devices require complex
video/image processing tasks leading to a very challenging design process; as it demands
more efficient and high processing systems. Neural networks are used in many of these 

 FPGA Implementation of Counter by Using State Look Ahead Logic
free download

JLVR Kumari, B Satheesh
ABSTRACT The main objective of this paper consists of the state look-ahead path and the
counting path. The proposed counter is a single mode counter, which sequences through a
fixed set of pre assigned count states, of which each next count state represents the next 

 High-Level Aging Estimation for FPGA-Mapped Designs
free download

High-Level Aging Estimation for FPGA-Mapped Designs Abdulazim Amouri and
Mehdi Tahoori FPL 2012  8 FPGA Users and Aging Estimation FPGA users cannot use
device-level aging models Aging also depends on the mapped design, resource usage 

 Performance and Analysis of Edge detection using FPGA Implementation
free download

RP Vignesh, R Rajendran ,ijmer.com
Abstract Edge detection serves as a pre-processing step for many image processing
algorithms such as image enhancement, image segmentation, tracking and image/video
coding. The edge detection is one of the key stages in image processing and object 

 FPGA Implementation of a 32k Point Accumulating FFT with 2 Gs/s Throughput
free download

B Stuber, D Zardet, AO Benz, C Monstein, H Meyer ,edit.ethz.ch
The FFT is realized in a single Xilinx Virtex field programmable gate array (FPGA) operating
at a clock speed of 125 MHz. The unit is able to process a continuous input data stream of 2
giga-samples per second (Gs/s). The input data width is 8 bit. Handling this enormous

 HARDWARE IMPLEMENTATION OF AN ANN TRAINED BY GA AND PSO BASED ON FPGA
free download

APDHAR Akkar, PDSSD Hasan
Abstract In this paper, Particle Swarm Optimization-feedforward Neural Network (PSONN)
and Genetic Algorithm-Neural Network (GANN) are proposed to enhance the learning
process of ANN in term of convergence rate and classification accuracy. They have been 

 Design and Implementation of DSSS-CDMA Transmitter and Receiver for Reconfigurable Links Using FPGA
free download

R Sarojini, C Rambabu
Abstract-Direct sequence spread Spectrum (DSSS), is also called as direct sequence code
division multiplexing (DS-CDMA). In direct sequence spread spectrum, the stream of
information to be transmitted is divided into small pieces, each of which is allocated across 

 FPGA-based data compressor based on Prediction by Partial Matching
free download

J Ratsaby, V Sirota ,ariel.ac.il
Abstract—We design and develop a data compression engine on a single FPGA chip that is
used as part of a text-classification application. The implementation of the prediction by
partial matching algorithm and arithmetic coding data compression is totally in hardware 

 Power Amplifier Behavioral Modeling by Neural Networks and their Implementation on FPGA
free download

RSN Ntouné, M Bahoura, CW Park ,www-mobile.ecs.soton.ac.uk
(FPGA) implementation of two power amplifier (PA) dynamic behavioral modeling
approaches with real-valued time-delay neural network (RVTDNN) and real-valued
recurrent neural network (RVRNN) architectures are presented. The proposed PA models 

 FPGA based Remote Monitoring System for Food Preservation
free download

S Rana, R Gill ,ijitee.org
Abstract-Food security is the assured access to adequate food that is nutritious, of good
quality, safe and meets cultural needs. In food production industries, performing visits for 24
hours evaluation is a difficult and time consuming process. In order to improve monitoring 

 SoC Simulator on FPGA using Bluespec System Verilog
free download

Abstract—Building large computing systems requires first to model them. Modern hardware
systems are so complex that their software models in the desired detail may be too slow.
Thus abstract hardware modelling can be appropriate. This paper presents an example 

 Concepts of Communication and Synchronization in FPGA-Based Embedded Multiprocessor Systems
free download

D Antonio-Torres ,cdn.intechopen.com
The advent of deep submicron (DSM) technologies has driven the evolution of very large
scale of integration (VLSI) chip design to new frontiers. In the early days, digital system
design was tackled as an integration of discrete systems in a printed circuit board (PCB), 

 Realization of Physical Downlink Control Channel (PDCCH) for LTE under SISO Environment using PlanAhead Tool and Virtex 5 FPGA
free download

SSA Abbas, G KS, SJ Thiruvengadam ,ijetae.com
Abstract- Long Term Evolution (LTE) permits mobile service providers to provide services in
an efficient manner such that the data rate is increased with a wider bandwidth. The control
channels of LTE include three channels namely Physical Downlink Control Channel ( 

 DEVELOPMENT OF AN FPGA-BASED REAL-TIME P300 SPELLER
free download

ABSTRACT A Brain Computer Interface (BCI) is a system that allows direct communication
between a computer and the human brain. Though the main application for BCIs is in
rehabilitation of disabled patients, they are increasingly being used in other application 

 Simulation and Analysis of Genetic Algorithm Based on FPGA
free download

B Umamaheswari, N Rajeswaran
Abstract In this paper, we propose a technique that utilizes the genetic algorithm for various
VLSI circuits. In GA, we proposed the method of automatic test pattern generation (ATPG) is
used to generate test vectors. Experiment results showed that the proposed algorithm 

 A FPGA Implementation of Memory Efficient Distributed Arithmetic Fir Filter
free download

V Narsipatnam ,ijcset.net
Abstract: Finite impulse response (FIR) filters are the most popular type of filters
implemented in software. An FIR filter is usually implemented by using a series of delays,
multipliers, and adders to create the filter’s output. To implement fir filter based on DA ( 

 FPGA Implementation of Optimized 4 Bit BCD and Carry Skip Adders using Reversible Gates
free download

BB Manjula, VS Sanganal, V Ravichandra ,2012
Abstract—The project proposes design of BCD adder and implementation of Carry Skip
adder using the new concept of Reversible logic gate to improve the design in terms of
garbage’s and area on chip. Furthermore, in the recent years, reversible logic has 

 A Distributed Canny Edge Detection and its FPGA Implementation
free download

S Prasath, S Umamaheswari ,journal.bonfring.org
Abstract—Edge detection is one of the basic operation carried out in many image
processing algorithms. The canny edge detection algorithm is most widely used algorithm
for edge detection process. In this paper, canny edge detection in distributed manner is 

 FPGA Based SOC for Railway Level crossing Management System
free download

R Ramachandran, JTJ Prakash ,International Journal of Soft Computing
Abstract-It is to develop the FPGA based, System on Chip (SOC) to implement the safety
system in Railways for level crossing. For the communication RF module [1] with the
coverage of large distance, that is Outdoor line-of-sight: up to 15 miles (24 km) with high 

 Design Neural Wireless Sensor Network Using FPGA
free download

BM Khammas
ABSTRACT Wireless sensor networks (WSN) are an exiting emerging technology that
scientists believe to become a part of every day life in the next few years. However, at this
time many issues in wireless sensor networks remain unresolved. This paper studies the 

 Design and FPGA Implementation of Hash Processor
free download

M Askar, TS Çelebi ,iscturkey.org
Abstract—Related to the tremendous developments in the wired and wireless
communications area, the demand for secure data transmission increases. In order to find
solutions for this increasing demand new algorithms and security standards are 

 An update on Scalable Implementation of Primitives for Homomorphic EncRyption–FPGAimplementation using Simulink
free download

Abstract Accellerating the development of a practical Fully Homomorphic Encryption (FHE)
scheme is the goal of the DARPA PROCEED program. For the past year, this program has
had as its focus the acceleration of various aspects of the FHE concept toward practical 

 Compression of FPGA Bitstreams–A Comparison
free download

MK Drisya, S Joseph
Abstract—In this paper, compression of fpga bit streams has been implemented. Bit stream
compression is important in reconfigurable system design since it reduces the bit stream
size and the memory requirement. It also improves the communication bandwidth and 



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