On the reuse of VHDL modules into systemC designs


On the reuse of VHDL modules into systemC designs-download

On the Reuse of VHDL Modules into SystemC Designs … The need of integrating new
designs with already existing modules may lead to the generation of heterogeneous models,
specifications, based both on SystemC and on VHDL (or Verilog)



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On the reuse of VHDL modules into systemC designs IEEE PAPER

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