On the reuse of VHDL modules into systemC designs

On the reuse of VHDL modules into systemC designs-download

On the Reuse of VHDL Modules into SystemC Designs … The need of integrating new
designs with already existing modules may lead to the generation of heterogeneous models,
specifications, based both on SystemC and on VHDL (or Verilog)

IEEE PROJECTS 2019

IEEE PROJECTS