Power Reduction in VLSI chips

Power Reduction in VLSI chips by Optimizing Switching Activity at Test Process, Architecture & Gate Level
C Sharma – International Journal of Engineering Science, 2011 –
Abstract: Due to increasing the demand of low power VLSI test process, it is necessary to
consider all small factors which affect on total power dissipation. This paper gives the
reduction of power by advancement in test pattern generation methods and gives the