Proof theory and a validation condition generator for VHDL
Proof theory and a validation condition generator for VHDL-download
PT Breuer, LS Fernandez… – Proc of the EURODAC, …, 1994 – cs.york.ac.uk
We present a Hoare-style programming logic for VHDL to- gether with a succinct PROLOG implementation
which acts as a validation condition generator. The logic is based on a particularly simple formalization
of the language as a pure side-effect on an infinite time-sequence of states. The PROLOG
COMMENT vlsi
Objective VHDL-tools and applications
Assessing the potential of multi-threaded VHDL simulation
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