SAR ADC architecture




SAR ADC architecture with digital error correction

FREE-DOWNLOAD [PDF] M Hotta, M Kawakami, H Kobayashi… – … on Electrical and …, 2010
This paper describes a high-performance successive approximation register (SAR) analog to
digital converter (ADC) using three comparators operating in parallel, instead of just one as in
conventional ADCs. This comparator redundancy enables potentially faster operation,




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