Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints


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FREE-DOWNLOADTE Yu, T Yoneda, K Chakrabarty… – Proceedings of the 2009
Abstract We present a thermal-aware test-access mechanism (TAM) design and test scheduling
method for system-on-chip (SOC) integrated circuits. The proposed method uses cycle-accurate
power profiles for thermal simulation; it also relies on test-set partitioning, test inter




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