ENGINEERING RESEARCH PAPERS

cmos vlsi IEEE PAPER 2017




Design and Implementation of Enhanced Leakage Power Reduction Technique in CMOS VLSI Circuits
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Abstract The rapid increase of semiconductor technology and growing demand for portable devices powered up through battery has led the constructors to scale down the feature size; resultant reduced threshold voltage as well as thereby enabling integration of incredibly

Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power
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Abstract The rise in technology has demanded the use of more and more components on chip. This rise has led to rise in power dissipation and a major challenge for circuit designers. Due to scaling, the reduction of threshold voltage in CMOS circuits increases the

Low Power Consumption Using CMOS VLSI Design in Modern Trends
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The revolution of wireless communication, portable and mobile devices has consistently demanding the designer to design the device for low power consumption. Power loss becomes a main parameter of integrated circuits, particularly for portable computers and

CMOS nanoelectrode array for all-electrical intracellular electrophysiological imaging
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Developing a new tool capable of high-precision electrophysiological recording of a large network of electrogenic cells has long been an outstanding challenge in neurobiology and cardiology. Here, we combine nanoscale intracellular electrodes with complementary metal-

Design and Implementation of Enhanced Leakage Power Reduction Technique in CMOS VLSI Circuits
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Abstract The rapid increase of semiconductor technology and growing demand for portable devices powered up through battery has led the constructors to scale down the feature size; resultant reduced threshold voltage as well as thereby enabling integration of incredibly

Design and Analysis of CMOS based Low Power Carry Select Full Adder
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ABSTRACT:-Carry Select Adder (CSLA) is trusted to be one of the most speedster adders used in many data-processing processors to achieve faster arithmetic functions. From the structure of the CSLA, it is predicted that there is scope for reducing the area and power

Modeling the CMOS Inverter using Hybrid Systems
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We are currently trying to determine the analog output of a CMOS inverter (see Figure 1) based on the analog input with as little effort as possible. Unfortunately an accurate formula Vout (Vin) can not be derived for the whole voltage range because the inverter, or more

A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11 n WLAN Applications
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Abstract A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11 n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output Abstract The control area network (CAN) wired communi-cation standard is becoming the bus of choice for many space applications. However, the severe− 2 to 7 V common-mode and− 3 to 16 V failure tolerance requirements of the CAN bus driver have restricted its

Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits
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ABSTRACT This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180-nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, currentsource sub-circuits with most of the

A Review on Pipe Line Analog to Digital Converter using 0.18 µm CMOS Technology
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ABSTRACT This work describes a 12-bit pipeline ADC (Analog-to-Digital Converter) for CMOS (Complementary Metal Oxide Semiconductor) that is implemented in a TSMC 0.18 μm CMOS process. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) The point where wireless communication and ubiquitous connectivity became an essential part of our lives is already past. Generation after generation communication speed is being taken to unprecedented levels, requiring both state-of-the-art hardware and software to

Low Power Full Adder Circuit Design Using Two Phase Adiabatic Static CMOS Logic
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Abstract: Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two-phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compares the power consumption of Static Energy Recovery Full Adder Abstract This paper presents a CMOS smart temperature sensor using a switched Vernier time-to-digital converter (SVTDC) to achieve an energy-efficient temperature sensing. The proposed temperature sensor employs two switched ring oscillators (SROs), of which the

8.25 μm Pitch 66% Fill Factor Global Shared Well SPAD Image Sensor in 40nm CMOS FSI Technology
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Abstract We present the first single photon avalanche diode (SPAD) device and image sensor realized in a customized 40nm CMOS front side illuminated (FSI) technology. The 96× 40 array utilizes a global shared well layout structure with up to 66% fill factor at 8.25 µm

Power Reduction through Different Low Power CMOS Technique in Power Gating Switch
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ABSTRACT In this thesis has introduced two new techniques for low CMOS switch circuit design techniques as Lector technique and Galeor technique for reducing the leakage power dissipation in CMOS switch circuit. low power CMOS switchs are performance CMOS integrated circuit design for wireless power transfer intends to report the state-of-the art analog and power management IC design techniques for various wireless power transfer (WPT) systems. To propose elaborate power management solutions, the circuit designers The future is the Internet of Things (IoT) and it is already here, eg, in the environmental monitoring, in the manufacturing, and in the building and home automation. By the technology of IoT, there have been millions of mobile devices that are collecting data and Investigation of post processing resistivity modification for HV- CMOS pixel detectors
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When a minimum ionising particle (MIP) passes through a semiconductor material, it will excite electrons creating electron-hole pairs (electrons as green arrows below). An external bias voltage increases the depletion region. In this region the current pulse is dominantly Broadband IQ CMOS transceivers for compact and ultra-compact NMR probes
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CMOS technologies allow for the miniaturization of the electronics needed for a pulsed NMR probe. Recently, use of single-chip transceivers was demonstrated for both compact NMR tools implementation and realization of ultra-compact high sensitivity sub-nL probes [1-4].

Design and Implementation of Two Stage CMOS Operational Amplifier
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Abstract-A method for fabricating and implementing a Two Stage CMOS Operational Amplifier using Cadence Virtuoso 180nm Technology is presented in this paper. The proposed CMOS op-amp is designed for 1.8 V power supply. Op-Amp is basically a DC-

A High Data Rate, High Output Power 60 GHz OOK Modulator in 90 nm CMOS
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Abstract In this paper, we present a 60 GHz on-off keying (OOK) modulator in a 90 nm CMOS . The modulator employs a current-reuse technique and a switching modulation for low DC power dissipation, high on/off isolation, and high data rate. The measured gain of

A Simple Static Noise Margin Model of MOS CML Gate in CMOS Processes
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Abstract This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Tradeoffs between speed and logic reliability are discussed,

Design and Evaluation of a CMOS Image Sensor with Dual-CDS and Column-parallel SS-ADCs
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(CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a fieldprogrammable gate array (FPGA) integrated module. The CIS is composed of a 320 x 240 pixel array with 3.2 μm x 3.2 μm

A CMOS -based Temperature Sensor with Subthreshold Operation for Low-voltage and Low-power On-chip Thermal Monitoring
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Abstract A CMOS -based temperature sensor is proposed for low-voltage and low-power on-chip thermal monitoring applications. The proposed temperature sensor converts a proportional to absolute temperature (PTAT) current to a PTAT frequency using an integrator Abstract. Latest nanometer CMOS technology nodes have highlighted new issues in security of cryptographic hardware implementations. The constant growth of the static power consumption has led to a new class of side-channel attacks. Common attacks exploiting

A 12-bit 2.88 mW 50MHz SAR ADC in 0.18 μm CMOS
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Abstract In this paper a 12-bit 2.88 mW 50MHz SAR ADC implemented in 180nm CMOS process is presented. A differential split CDAC is adopted which eliminates mismatch of the capacitors. A high-speed and highresolution dynamic latch comparator is designed to save

CMOS Analog Integrate-and-fire Neuron Circuit for Driving Memristor based on RRAM
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Abstract We designed the CMOS analog integrate and fire (I F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have HfO2 switching layer using atomic layer deposition (ALD). The

Analysis and Design of a Low Power and Wide Tuning Range Voltage-Controlled Ring Oscillator in 45 nm CMOS Process
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Abstract This Paper reports on design and analysis of CMOS Voltage Controlled Ring Oscillator (VCRO) based on the delay cells proposed by Changzhi Li and Jenshan Lin. The two stage CMOS VCRO exhibits very low power consumption and wide tuning range when

Low Noise CMOS Temperature Sensor with On-Chip Digital Calibration
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In this paper, we present a low-noise CMOS temperature sensor with an on-chip digital calibration circuit. The low-voltage bandgap reference circuit is designed to generate current proportional to absolute temperature (PTAT) using a parasitic NPN bipolar junction transistor

High Performance Spin-Orbit-Torque (SOT) Based Non-volatile Standard Cell for Hybrid CMOS /Magnetic ICs
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Abstract Spin-orbit-torque magnetic tunnel junction (SOT-MTJ) is an emergent spintronics device with a promising potential. It resolves many issues encountered in the current MTJs state of the art. Although the existing Spin Transfer Torque (STT) technology is

A CURRENT MIRROR BASED TWO STAGE CMOS CASCODE OP-AMP FOR HIGH FREQUENCY APPLICATION
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Abstract This paper presents a low power, high slew rate, high gain, ultra wide band two stage CMOS cascode operational amplifier for radio frequency application. Current mirror based cascoding technique and pole zero cancelation technique is used to ameliorate the

Characterization of 6T CMOS SRAM in 65nm and 120nm Technology using Low power Techniques
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Abstract-As the channel length of MOSFETs is scaling down, the Power dissipation of the SRAM cells become the major concern for future technology. In this paper, stable SRAM cells power dissipation reduction in 6T static random access memory (SRAM), is described Impulse-based ultra-wideband (UWB) systems, notably unlicensed UWB systems operating across or within 3.1 10.6 GHz, are unique systems possessing many desired characteristics, owing to the transmission and reception of only a single signal having pulse

Linear CMOS Power Amplifier for WiMAX Application
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Abstract CMOS power amplifier is field of interest of developers now a days due to high demand of mobility requirement with higher data transfer speed. Pas are the most power consuming part and main contributor in transceiver chain. Since we have limited power

A Switched VCO-based CMOS UWB Transmitter for 3-5 GHz Radar and Communication Systems
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Abstract A switched VCO-based UWB transmitter for 3-5 GHz is implemented using 0.18 μm CMOS technology. Using RF switch and timing control of DPGs, the uniform RF power and low power consumption are possible regardless of carrier frequency. And gate control of Simulation tutorial on HV/HR- CMOS TCAD and Geant4 simulations
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The AIDA-2020 Advanced European Infrastructures for Detectors at Accelerators project has received funding from the European Unions Horizon 2020 Research and Innovation programme under Grant Agreement no. 654168. This work is part of AIDA-2020 Work Package 6: Novel Almost on a daily basis, nanoeletronic metal-oxide-semiconductor ( CMOS ) technology and device design are introduced and explored in rapidly developing semiconductor industry. This book 3D TCAD Simulation for CMOS Nanoeletronic Devices presents a self-contained

CMOS VDIBAs-Based Single-Resistance-Controlled Voltage-Mode Sinusoidal Oscillator
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Abstract In this communication, a new single-resistance controlled sinusoidal oscillator (SRCO) has been presented. The presented SRCO uses two voltage differencing inverting buffered amplifiers (VDIBAs), one resistor and two capacitors in which one is grounded (GC)

Millimeter-wave CMOS Transceiver Techniques for Automotive Radar Systems
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Recently, advanced driver assistance systems (ADAS) with the keyword of safety have attracted attention in the world. Many mega-suppliers (Tier 1) and the others have been carrying out development for safe systems using cameras, lasers, and millimeter-wave radar

An Analysis of Novel CMOS Ring Oscillator Using LECTOR Technique with Minimum Leakage
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ABSTRACT when we require developing digital integrated circuits, then we are facing many challenges like the way of greater energy consumption. The mixture of minor procedure geometries, greater functional integration and higher clock speed shave contributed to

CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies
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Abstract This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. Dear editor, It becomes practical to implement competitive mm-wave circuits in advanced deep-submicron CMOS process, with the scaling CMOS technology and innovative circuit techniques. Among various mm-wave circuit blocks, the oscillator draws special attention

A Low Power and Linear Voltage Controlled Oscillator Using Hybrid CMOS -CNFET Technology
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Abstract This paper presents a hybrid CMOS -CNFET voltage controlled oscillator (VCO) with low power dissipation and linear response over a wide control voltage range. The hybrid circuit is based on PTM 32nm low power CMOS devices and 32nm CNFET devices with

Exploration on Power Delay Product of Basic Logic Gates for Various CMOS Logic Styles
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Abstract Since Power dissipation is one of the important criteria in Low power VLSI design, Chip designers are making lot of efforts to reduce the power dissipation. The power efficiency of any architecture can be explained in terms of power delay product. The circuit

Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder
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Abstract This paper proposes a new full adder design based on pass-transistor logic that offers ultralow power dissipation and superior variability together with low transistor count. The passtransistor logic allows device count reduction through direct logic realization, and

A CMOS Morlet Wavelet Generator
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Abstract. The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a low power consumption, improve standard deviation (σ) control and also have a small form factor. A

CMOS Bridge Rectifier (CBR) using 0.18 Micron Technology for Energy Harvesting Applications
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Abstract-In this work, an input-powered AC/DC CMOS bridge rectifier (CBR) is proposed using 0.18 µm CMOS process. It is based on a simple bridge connected full wave rectifier, without an external dc voltage to turn-ON. The rectifier may be used for energy harvesting

Design of Digital Circuits for ECG Data Acquisition System Using 90nm CMOS Technology
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ABSTRACT Day by day the scope use of the electronics concepts in bio-medical field is going to increase step by step. Electrocardiogram (ECG) is basically a non-invasive way of measuring the electrical activity of the heart by registering the extracellular potentials

Fixed Pattern Noise pixel-wise linear correction for crime scene imaging CMOS sensor
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ABSTRACT Filtered multispectral imaging technique might be a potential method for crime scene documentation and evidence detection due to its abundant spectral information as well as non-contact and non-destructive nature. Low-cost and portable multispectral crime

A CMOS Tracking System Approach for Cell Motility Assays.
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Abstract: This work proposes a method for studying and monitoring in real-time a single cell on a 2D electrode matrix, of great interest in cell motility assays and in the characterization of cancer cell metastasis. A CMOS system proposal for cell location based on occupation maps

Design of Multiplier using Low Power CMOS Technology
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ABSTRACT The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This

Design of DPLL Using Sub-Micron 45 nm CMOS Technology and Implementation Using Microwind 3.1 Software
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Abstract: Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind

Improved Two Phase Clocked Adiabatic Static CMOS Logic Circuit
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ABSTRACT This paper proposes an improved Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed circuit is based on energy recovery adiabatic principle which consumes less power. The number of transistor required in proposed circuit is same

Dual mode 4th order active-RC low-pass filter with tunable cut-off frequency from 3 MHz to 20 MHz in 65 nm CMOS
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Abstract. In this paper, a 4th order active-RC filter with two approximation modes and a tunable bandwidth from 3 MHz to 20 MHz is presented. The filter can be configured to achieve maximally flat in-band magnitude or phase response by using a dual mode resistor

COLUMN LEVEL TWO-STEP MULTI-SLOPE ANALOG TO DIGITAL CONVERTER FOR CMOS IMAGE SENSORS
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The design is realized for pixel pitch of 6.7 µm. Power consumption per column ADC is 88 µW and sampling speeds larger than 50kS/s is supported. The prototype IC generates timing and biasing signals on its own. Using SPI interface, bias voltages can be trimmed with the

Radiation Tolerance Evolution of CMOS Integrated Circuits
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Abstract: One of the main causes of environmental damage to the electronic components that have to operate in space missions has been historically the space radiation. This has determined the need to apply special conditions in the design, manufacture and qualification Bilateral Dual-Frequency-Combs-Based 220-to-320GHz Spectrometer in 65-nm CMOS for Gas Sensing
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Millimeter-wave/terahertz rotational spectroscopy offers an ultra-wide detection range of gas molecules for chemical and biomedical sensing. The linewidth of the absorption spectrum, limited by the Doppler effect of molecules, has a quality factor near 106, indicating absolute

Design of Ultra Low Power CMOS Inverter
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Abstract: The major concern in the designing of low power designs are energy consumption and design flexibility. Power dissipation, delay and area can be reduced with the help of scaling technology. Now a day the devices with ultra low power and area efficient designs

Delay Depreciation and Power efficient Carry Look Ahead Adder using CMOS
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Adder is the major component in all data path unit. In this paper, designing of fast adder has been done by carry look ahead adder instead of ripple carry adder. Since the RCA has worst propagation delay of carry bit. Power and area remain the main constraint in designing of

A PIONEER APPROACH TO MITIGATE LEAKAGE POWER IN CMOS CIRCUIT
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ABSTRACT In this fast growing age of semiconductor technology, the research field has been entered in nano-scaled or ultrathin regime. Various microcontroller based digital devices are required efficient switching speed, better noise immunity and minimum power

INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES RESEARCH TECHNOLOGY IMPROVEMENT IN NOISE AND DELAY IN DOMINO CMOS LOGIC
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ABSTRACT New experiments are always welcomed in the field of chip designing in VLSI technology. VLSI is advanced innovation over solid state devices and is based on CMOS designing. CMOS is a combination of PMOS and NMOS. The CMOS technology is mostly

Design of a 1GHz Voltage Control Oscillator for PLL using 0.18 µm CMOS Technology
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ABSTRACT This paper presents a design technique of efficient wide frequency range voltage control oscillator (VCO). An implementation of five stage CMOS VCO in Tanner S Edit environment with high oscillation frequencies for different input control voltage (DC)

How to Design Battery-Assisted Photovoltaic Switched-Inductor CMOS Charger Supplies
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Abstract Wireless microsensors can sense and share data that can save lives, energy, and money. Recharging or replacing thousands of tiny, easily exhaustible batteries, however, is too costly. Fortunately, photovoltaic (PV) cells can generate 100× more power from sunlight Supporting Information: Visible Wavelength Color Filters using Dielectric Subwavelength Gratings for Backside-illuminated CMOS Image Sensor Technologies
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Figure S2: RCWA simulations of the angular dependence of the transmission spectra under unpolarized light illumination for the two cases:(a) with and (b) without SiO2 spacers). The figures indicate that the angular dependence mainly arises from the angular response of the

Evaluation of Inverter Reliability Performance Due to Negative Bias Temperature Instability (NBTI) Effects in Advance CMOS Technology Nodes
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ABSTRACT Negative bias temperature instability (NBTI) is the most concern issue CMOS devices with the scaling down of the CMOS technologies. NBTI effect contributes to P MOSFET device degradation which later reduce the performance and reliability of CMOS

Modeling of a CMOS Convective Accelerometer for HDL integration
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Abstract This paper introduces an analytical modeling of a convection heat CMOS accelerometer. The modeling approach relies on the use of fundamental results and is validated using both experimental data issued from test vehicles and FEM analysis. Since

DESIGN OF LOW POWER SAR ADC FOR ECG USING 45nm CMOS TECHNOLOGY
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ABSTRACT Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power Muon-Drift-Tubes detectors is hereby presented (defined 8xAFE). The system is composed by the cascade of the analog signal processing Front-End and of the Wilkinson A/D, performing both Time-over-Threshold (ToT) and charge measurement. The sensitivity at the

CMOS AND DTMOS SENSE AMPLIFIER FOR SRAM APPLICATION
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Abstract: In this paper comparison between CMOS and DTMOS amplifiers for SRAM application using 180nm technology is done. The tool used for simulation is Cadence Tool. The power dissipation varies with variation in supply voltage. The delay and average power

A Multi-phase VCO Quantizer based Adaptive Digital LDO in 65nm CMOS Technology
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Abstract A digital low-dropout (DLDO) voltage regulator circuit is proposed utilizing a multi phase VCO based time quantizer. This high-resolution quantizer requires much lower sampling clock frequency compared to the previously proposed 1-bit comparator based

A 0.5 e-rms Temporal-Noise CMOS Image Sensor with Charge-Domain CDS and Period-Controlled Variable Conversion-Gain
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Abstract This paper introduces a proof-of-concept low-noise CMOS image sensor (CIS) intended for photon-starved imaging applications. The proposed architecture is based on a charge-sampling pixel featuring in-pixel amplification to reduce its inputreferred noise. With

A REVIEW ON PIPE LINE ANALOG TO DIGITAL CONVERTER USING 0.18 µm CMOS TECHNOLOGY
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ABSTRACT This paper describes a 12-bit pipeline ADC (Analog-to-Digital Converter) for CMOS (Complementary Metal Oxide Semiconductor) that is implemented in a TSMC 0.18 μm CMOS process. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ)

Design of a CMOS OR Gate using Artificial Neural Networks (ANNs)
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Abstract:-This paper is an approach to simplify the electronic circuits by using Complementary Metal Oxide Semiconductors ( CMOS ) transistors and map those to equivalent Artificial Neural Networks (ANNs). The implementation of those circuits in ANN

Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power
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Abstract The rise in technology has demanded the use of more and more components on chip. This rise has led to rise in power dissipation and a major challenge for circuit designers. Due to scaling, the reduction of threshold voltage in CMOS circuits increases the

A Low Phase Noise Wide Tuning Range CMOS Differential Ring Voltage Controlled Oscillator for Signal Processing
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Abstract-This paper presents a detailed two stage ring oscillator in CMOS standard 45nm technology. This VCO operates in the range of 2.5 GHz to 7.7 GHz. Along with that low phase noise and low power consumption is estimated in this circuit. It operates at very low

A photonic interconnect layer on CMOS
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Abstract We propose and demonstrate a photonic interconnect layer consisting of heterogeneous microdisk lasers and microdetectors integrated with a nanophotonic silicon waveguide circuit. The photonic layer is fabricated using waferscale processes and a die-to-

An Ultra-Wide-Band 2.66-3.75 GHz LNA in 0.18-µm CMOS Radio Frequency
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Abstract An Ultra-Wide-Band Low Noise Amplifier is designed in this work. The designed LNA is of two stages that may be used in various applications in communication systems. The designed LNA is simulated by HSPICE in 0.18-μm CMOS Radio Frequency technology.

Design of 16 bit 180nm CMOS Fully Segmented DAC
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Abstract: Due to increasing advancement in technology in the field of digital signal processing, data converters such as analog to digital converters and digital to analog converters with high resolution are profoundly required but problem with incorporating these

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