10-bit 50-MS SAR ADC in CMOS Process
This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13µm 1P8M CMOS technology, the ADC only occupies 0.075mm
In conventional successive approximation register (SAR) ADCs, the primary sources of power dissipation are the digital control circuit, comparator and the DAC capacitor array. The digital power reduces with advancement of technology. However, the power of comparator and capacitor network is limited by mismatch and noise issuesˁRecently, several energy-efficient switching methods  have been presented to reduce the switching energy of the DAC capacitor network. These works reduce the unnecessary energy wasted in switching sequence. However, the SAR control logic becomes more complicated due to the increased capacitors and switches. This work proposes a set-and-down switching method to save the power consumption in switching procedure without splitting or adding any capacitors and switches. In addition, the method also improves the settling speed of the DAC.
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