45nm High-k+ metal gate strain-enhanced transistors
FREE-DOWNLOADC Auth, A Cappellani, JS Chun… – VLSI Technology, …, 2008
Two key process features that are used to make 45nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193nm dry lithography to the 45nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45nm high-k + metal gate technology