A Formalization of a Subset of VHDL in the Boyer-Moore Logic

A Formalization of a Subset of VHDL in the Boyer-Moore Logic-download

Abstract. We present a mathematical definition of a hardware description language that admits
a semantics- preserving translation to a subset of VHDL. The language is based on the VHDL
model of event-driven simulation and includes behavioral and structural circuit

A Formalization of a Subset of VHDL in the Boyer-Moore Logic IEEE PAPER

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