adc-analog to digital converter research papers 2012

 A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm 2 and 500 mW in 40 nm Digital CMOS
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CY Chen, J Wu, JJ Hung, T Li, W Liu ,IEEE J. Solid-State , 2012 ,
? Fig. 4 shows the block diagram of the SHA circuit? The amplifier output common-mode
voltage Vcm1 and input common-mode voltage Vcm2 track over process, supply voltage,
and temperature (PVT) variations for optimal operating points? The switch that turns on ..

 New Multiplier for a Double-Base Number System Linked to a Flash ADC
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MS Nguyen, I Kim, K Choi, J Lim, W Choi, J Kim ,ETRI Journal, 2012
The double-base number system has been used in digital signal processing systems for
over a decade because of its fast inner product operation and low hardware complexity. This
letter proposes an innovative multiplier architecture using hybrid operands. The multiplier 

 A 1-V 15-Bit Audio S-ADC in 0.18 µm CMOS
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L Liu, D Li, L Chen, Y Ye, Z Wang ,IEEE Transactions on Circuits , 2012 ,
Abstract—In this paper a 1V 15-bit ?S ADC for audio application is presented. Second order
modulator with feedforward path is adopted in order to reduce the swing of each integrator.
Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is 

 Designing Power Supplies for High Speed ADC
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R Reeder ,2012 ,
This technical article describes techniques to measure a converter’s AC power supply
rejection, thereby establishing a baseline for the converter’s power supply noise sensitivity.
A simple noise analysis of an actual power supply is given to show the user how to apply 

 VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology
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MRM Shende, PR Gumble ,International Journal, 2012
Abstract Analog-to-digital converters (ADCs) are key design blocks and are currently
adopted in many application fields to improve digital systems, which achieve superior
performances with respect to analog solutions. Application such as wireless 

 A Low-power Pipeline ADC with Front-end Capacitor-sharing
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G Zhang ,2012 ,
Abstract This thesis presents the design and experimental results of a low-power pipeline
ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5
bits/stage, and is implemented in IBM 0.13 µm technology. The purpose of the technique 

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H Vishwakarma, MR Sreevatsava, R Krishnamurthy ,2012 ,
Digital VLSI design VLSI Design Lab ABV-IIITM Gwalior TM2B and BEC FOR FLASH ADC by
Harsh Vishwakarma (2011VLSI-11) MRSreevatsava (2011VLSI-12)  ABV-IIITM Gwalior

 A Pseudo 12-bits 8, 33MS/s Charge Redistribution Successive-Approximation ADC in CMOS 65nm for Image Sensors
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MA Marktani, A Ahaitouf, A Ahaitouf, S Vivien ,IJCSNS, 2012 ,
Summary A new charge redistribution Successive Approximation AD Converter (SA ADC)
potentially suitable for array implementation in CMOS Imagers is presented. The
performances achieved exceed the performances of the actual sensors in terms of both 

 Design of Chip for Flash ADC application of MCML in 180nm Technology
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R Moud, DB Ojha ,2012 ,
ABSTRACT This report describes how MOS Current-Mode Logic (MCML) based circuits
components where designed and created, in order to implement a six bit flash ADC. A short
introduction about MCML circuits is given, as well as a complete description of speed-to- 

 Interfacing the Embedded 12-Bit ADC in a TMS570LS31x/21x and RM4x Series Microcontrollers
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H Weng ,2012
ABSTRACT The Texas Instruments Hercules™ ARM® Safety Microcontrollers
TMS570LS31x/S21x and RM4x series of products have two 12-bit analog-to-digital
converters (ADC). This document provides the device configuration and layout 

 Use a switching regulator to power a high-speed ADC
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T Neu, T INSTRUMENTS ,EDN-Electronic Design News, 2012
POWER9SUPPLY FILTERING A key component in isolating the switching noise from the
ADC is the power-supply filter, which comprises a ferrite bead and the bypass capacitors.
You should consider several critical characteristics when choosing a ferrite bead. First, the 

 High level simulation of multiplexed incremental ADC for Integrated Power Meter
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D Mirkovic, P Petkovic ,
Abstract–This paper presents an architectural solution for multiplexed ADC designed for a
new generation of integrated power meter, IMPEG3. Basic problems related to the use of
classic S? ADCs will be discussed. Proposed solution along with appropriate procedure 

 A 2.9-mW 11-b 20-MS/s Pipelined ADC with Dual-Mode-Based Digital Background Calibration
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N Sun, HS Lee, D Ham ,
Abstract—We report an 11-b 20-Ms/s pipelined ADC in 0.18-µm CMOS with a novel dual-
mode-based digital background calibration method that altogether corrects errors caused by
gain insufficiency, gain nonlinearity, and capacitor mismatches. The calibration enables 

 FPGA Based Hardware Efficient Digital Decimation Filter for?-? ADC
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SK Maity, HS Das ,signal processing
Abstract—This paper focuses on the design of a FPGA based off chip digital decimation filter
for single bit sigma-delta A/D converter with medium oversampling ratio for the processing of
audio signal. A second-order single-stage sigma-delta (?-?) modulator with single bit 

 Design of OTA with Common Drain and Folded Cascade Used in ADC
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G Wei, G Wei
Abstract—In this report, an OTA which is used in fully differential pipelined ADC was
described. Using gain-boost architecture with difference-ended amplifier, this OTA achieve
high-gain and high-speed. Besides, the CMFB circuit is also used, and some methods are 

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C BENNICI ,Acta Medica, 2012 ,
The technique of spreading measures the degree of diffusion of water molecules in biological
tissues and this degree is one of the flow characteri- stics of the MR signal(1.2). The technique
has been used primarily in the field neuroradiological, in particular for the diagno- sis of 

 Analog Multitone with Interference Suppression: Relieving the ADC Bottleneck for Wideband 60 GHz Systems
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H Zhang, S Venkateswaran, U Madhow ,
Abstract—Commercial exploitation of the large amounts of unlicensed spectrum available at
60 GHz requires that we take advantage of the low-cost digital signal processing (DSP)
made available by Moore’s law. A key bottleneck, however, is the cost and power 

 3.5-bit Stage of the CMOS Pipeline ADC
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G Wei, X Minglu, X Yan, Z Xiaotong, W Xinghua
Abstract—A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main
part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked
and designed are shown in details. Besides, an OTA which is used in fully differential 

 ADC based timing jitter estimation
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D Efstathiou
Abstract—A low aperture jitter specification of an ADC is critical to achieving high levels of
signal-to-noise ratios (SNR). ADCs are available with aperture jitter specifications as low as
70-fs rms. Extremely low jitter sampling clocks must therefore be utilized so that the ADC 

 Efficient Fault Effect Extraction for an Integrated Power Meter’s S? ADC
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Abstract-Analog to digital converter (ADC) is the vital part of many mixed-signal ICs because
it interfaces analog signals from real world with digital logic on a chip. Errors made during
conversion are hard to eliminate in the digital part that follows. Therefore, functional 

 Subcarrier Power Allocation in OFDM with Low Precision ADC at Receiver
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Abstract—Orthogonal frequency division multiplexing (OFDM) has been incorporated in
standards/draft standards such as IEEE 80.15. 3c, IEEE 802.11 ad for building multi-Gigabit
systems operating in a few GHz of bandwidth. The digital implementation of the receivers 

 Considerations for driving the reference pins on programmable gain amplifiers By Matthew Hann, SAR ADC Product Line Manager, Precision Analog, Texas
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M Hann ,
Programmable gain amplifiers (PGAs) are specialized amplifier configurations (Figure 1)
with trimmed internal resistor networks that offer improved performance over amplifiers used
with discrete resistor components. As is shown by the transfer functions of the PGAs in 

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Abstract—The performance of a pipelined ADC is mainly influenced by errors like gain error,
op amp non linearity and capacitor mismatches. The operational amplifier non linearity can
be reduced by calibration techniques to achieve high accuracy. The least mean squared ( 

 High Speed Continuous-Time Bandpass S? ADC for Mixed Signal VLSI Chips
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PA HarshaVardhini, M MadhaviLatha ,International Journal
ABSTRACT With the unremitting progress in VLSI technology, there is a commensurate
increase in performance demand on analog to digital converter and are now being applied
to wideband communication systems. sigma Delta (S?) converter is a popular technique 

 Compensating Signal Generators for a Self-Calibrating Tracking Adc
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Abstract–This thesis introduces the possibilities of constructing of compensating signal
generators for multi-bit self-calibrating tracking Analog-to-Digital Converter (ADC) on the
basis of Digital-to-Analog Converter (DAC) with weight redundancy. In the paper we show 

 Design and implementation of 4-bit flash ADC using folding technique in cadence tool
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SD Panchal, SS Gajre, VP Ghanwat
ABSTRACT—In this paper, we design a pipelined flash Analog-to-Digital Converter (ADC) to
achieve high speed using 0.18 umCMOS technology. The results obtained are also
presented here. The physical circuit is more compact than the previous design. Power, 

 Powering a Dual Supply Precision ADC with Switching Regulators
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R Du ,
Compared with an LDO device, a switching regulator always dissipates much less heat and
provides higher efficiency. Therefore, a switching regulator is suitable for powering different
kinds of portable devices or the nodes in a wireless sensor network to lengthen battery 

 Designing High Speed Flash ADC by Optimizing its Components
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A Mishra, VK Pandey, K Chaudhary ,
Abstract: In this paper we present the design methodology of high speed Flash ADC by
individually optimizing its various components so that the overall performance of the
resulting Flash ADC is improved over tradition0al Flash ADC’s. Together with high speed 

 Implementation of the onboard ADC and DAC on the Spartan 3E FPGA platform
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S Mascharak ,
ABSTRACT The objective of this project is to first interface the onboard ADC and DAC
available in the Spartan 3E FPGA platform, so that the real signals too can be processed by
the FPGA board. Thus first of all, the ADC was interfaced and the results were observed 

 Pipelined ADC Digital Calibration by Using Polynomial Inverse Function
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H Mafi, H Shamsi, NM Saei ,
Abstract—In this paper, a novel and simple digital technique to correct pipelined ADC errors
is presented. The technique uses an inverse function for the entire ADC. Linearity of the
ADC is improved by simultaneously adjusting the digital gain of the stages and the 

 High Speed Low Power Flash ADC Design for Ultra Wide Band Applications
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M SenthilSivakumar, M Banupriya
Abstract—This paper presents a high speed low power flash ADC design for applications
such as radar detection and wide band radio receivers. The flash ADC architecture consists
of a sample and hold circuit, preamplifier, comparator and digital decoder to perform a 

 Design of Low Power Sigma Delta ADC
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MA Sohel, KCK Reddy, SA Sattar ,International Journal
ABSTRACT A Low power discrete time sigma delta ADC consisting of a second order sigma
delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The
second order modulator is designed to work at a signal band of 20K Hz at an 

 Applications Of ADC In FPGA Implementation Of LMS Algorithm For Audio Applications
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SM Sakhare, SS Godbole, SB Pokle ,
Abstract-Adaptive filtering techniques are used in a wide range of applications. Adaptive
noise canceller is one of the most interesting applications for adaptive filters, especially for
the Least Mean Square (LMS) algorithm, due to its strength and calculus simplicity. Noise 

 Data-Weighted Averaging Technique for Sigma-Delta ADC with Segmented DAC
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S Jahangirzadeh, E Farshidi
Abstract—Data weighted averaging algorithm work well for relatively low quantization levels,
it begin to present significant problems when internal quantization levels are extended
farther. Each additional bit of internal quantization causes an exponential increase in the 

 A 12b 100MS/s Highly Power Efficient Pipelined ADC for Communication Applications
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SA Zahrai, SJ Azhari ,
ENOB is proposed for communication applications especially for Wireless Networks. The
proposed ADC achieves low power, high resolution and high speed operation due to
deliberately design of a low power high performance operational amplifier for the pipeline 

 On-chip Design Techniques for Reducing Power Supply Noise Effects on ADC with Chip-PCB Hierarchical Structure
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B Bae, J Cho, J Kim ,
Abstract—In this paper, we propose the on-chip design techniques for controlling Power
Supply Noise (PSN) effects on Analog-to-Digital Converter (ADC) with chip-Printed Circuit
Board (PCB) hierarchical structure interconnected by bonding wires. There are two steps 

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