ADC Error Testing


A Method for ADC Error Testing and its Compensation in Ratiometric Measurements

FREE-DOWNLOAD [PDF] K Hariharan, P Vasanthakumar, G Varun Measurement Science , 2010

Identification of unified ADC error model by triangular testing signal
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Modelling of the integral nonlinearity by the unified behavioural error model expressed as one dimensional image in the code k domain requires a minimal number of the error parameters. The unified error model consists of low and high code frequency components

How the voltage reference affects ADC performance, Part 2
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This article is Part 2 of a three-part series that investigates the design and performance of a voltage-reference system for a successive-approximation register (SAR) analog-todigital converter ( ADC ). A simplified version of this system is shown in Figure 1. When a design

The good, the bad, and the ugly aspects of ADC input noise Is no noise good noise
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All analog-to-digital converters (ADCs) have a certain amount of input-referred noise modeled as a noise source connected in series with the input of a noise-free ADC . Input- referred noise is not to be confused with quantization noise which only occurs when an ADC

Reducing ADC quantization noise
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Analog-digital converters (ADCs) are useful, and interesting, devices. ADCs perform amplitude quantization of an analog input signal into binary output words of finite length, normally in the range from 6-bits to 18-bits, and this amplitude quantization makes their

Fast gesting of ADC using unified error model
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The progress in the technology of the analogue to digital converters (ADCs) suppresses the error effects linked with its inherent architecture. Multiperiodicity of differential nonlinearity and the impact of analog components at the ADC input on the integral nonlinearity prefers

Maximum likelihood estimation of ADC parameters from sine wave test data
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The sine wave test is maybe the most important method for characterizing ADCs . By this, the acquisition device is excited with a sinusoidal signal, and a long series of output values is measured. With the help of these observations, the parameters of the DUT can be

Defining and testing dynamic ADC parameters
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77 structed from digital samples, the SNR is the ratio of a root-meansquare (RMS) full-scale analog input to its RMS quantization error, AQUANTIZATION [RMS]= ALSB/(12) 0.5= AREF/(2N (12) 0.5. The RMS value of a sine wave is one-half its peak-to-peak value divided

Conversion rate improvement of SAR ADC with digital error correction
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This paper describes a conversion rate of a high-performance successive approximation (SAR) ADC using three comparators operating in parallel, instead of just one as in conventional ADCs. This comparator redundancy enables faster operation, higher reliability

ADC architectures V: Pipelined subranging ADCs
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The pipelined subranging ADC architecture dominates todays applications where sampling rates of greater than 5 MSPS to 10 MSPS are required. Although the flash (all-parallel) architecture (see Tutorial MT-020) dominated the 8-bit video IC ADC market in the 1980s

Rules of the Road for High-Speed Differential ADC Drivers
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As applications engineers, we are constantly bombarded with a variety of questions about driving high-speed analog-to-digital converters (ADCs) with differential inputs. Indeed, selecting the right ADC driver and configuration can be challenging. To make the design of

High Resolution Noise Radar without fast ADC
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Conventional digital signal processing scheme in noise radars has certain limitations related to combination of high resolution and high dynamic range. The bandwidth of radar signal defines range resolution of any radar: the wider the spectrum the better the resolution. In

Measure flash- ADC performance for trouble-free operation
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Although manufacturers have expanded the number of guaranteed specifications they put on their data sheets, the test conditions often wont match those of your system design. You can use the methods de-scribed in Part 2 of this series to test a flash A/D converter, but the

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DESIGN OF THREE BIT ANALOG-TO-DIGITAL CONVERTER ( ADC ) USING SPATIAL WAVE- FUNCTION SWITCHED (SWS) FETS Abstract The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap quantum well channels inside the

Using redundancy to break the link between accuracy and speed in an ADC
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A M-Analog redundancy breaks the link between accuracy and speed in analog circuits. This technique has particular relevance IO analog to digital conversion. As feature size and supply voltage shrink, calibration based on redundancy of flash analog-to-digital converlers

Experimental verification of different models of the ADC transfer function
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The performance of current devices is mostly limited by the analogue front-end and analogue-to-digital converters ( ADC ) imperfections. ADC performance is not, as commonly known, ideal. One of the most important parameters is the nonlinearity, which if it is known

ADC Architectures IV: Sigma-Delta ADC Advanced Concepts and Applications
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In our discussion of Σ- ADCs up to this point, we have made the assumption that the quantization noise produced by the Σ- modulator (see Figure 1) is random and uncorrelated with the input signal. Unfortunately, this is not entirely the case, especially for the first-order modulator. Consider

Large scale error reduction in dithered ADC
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The combination of dithering and correcting table is the way of improvement not only of ADC resolution but also of linearity-effective number of bits. Dithering is used to reduce small- scale errors, such as quantization error, while correcting table reduces large-scale errors

ADC architectures I: the flash converter
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Commercial flash converters appeared in instruments and modules of the 1960s and 1970s and quickly migrated to integrated circuits during the 1980s. The monolithic 8-bit flash ADC became an industry standard in digital video applications of the 1980s. Today, the flash

A comparison of ADC dynamic test methods
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In this paper a comparison of the three most common test methods used on dynamic ADC testing is presented. This comparison is centred on three main figures of merit: functional performance characterisation parameters provided by the method, test implementation

An analog counter architecture for pixel-level ADC
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Pixel-level ADC is often used for applications that does not require small pixel (IR and X-ray imaging). In that case, the pixel changes a charge packet into a pulse that feeds the input of its own counter. This paper presents the advantages of an analog counter against a digital CSE PROJECTS