ADC in 65-nm

A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS

FREE-DOWNLOAD [PDF] J Yang, TL Naing… – Custom Integrated Circuits …, 2009
An asynchronous 6bit 1GS/s ADC is achieved by time inter- leaving two ADCs based on binary
successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous
technique eliminates the high internal clocks and significantly speeds up the SA