Asynchronous FPGA


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Variation Tolerant Asynchronous FPGA

FREE-DOWNLOAD [PDF] HS Low, D Shang, F Xia… – 2010
It is normally called logic cell (LC) in Xilinx the equivalent from Altera is called  PLE implementation
was constructed through the Cadence design process on UMC 90nm CMOS technology. Analog
simulations show that the circuit works as designed without logic errors within the 




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