BUFFER INSERTION IN VLSI ROUTING



A BINARY PARTICLE SWARM OPTIMIZATIONAPPROACH FOR BUFFER INSERTION IN VLSI ROUTING
FREE DOWNLOAD [PDF] 

ABSTRACT. Time delay in very large scale integration circuit routing can be improved using
several techniques such as intelligent selection of the size of wire and buffer, and strategic
buffer placement. This paper proposes the use of Binary Particle Swarm Optimization to



IEEE PROJECTS
COMMENT free research papers, vlsi



 

FREE IEEE PAPER