Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques
FREE-DOWNLOAD G Mariani, G Palermo, C Silvano… – … , and Simulation, 2009. …, Abstract—Multi-processor Systems-on-chip are currently de- signed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques
FREE-DOWNLOAD G Mariani, G Palermo, C Silvano… – … , and Simulation, 2009. …, Abstract—Multi-processor Systems-on-chip are currently de- signed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned to find the best trade-offs in terms of the selected system figures of merit (such as energy, delay
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints
FREE-DOWNLOADTE Yu, T Yoneda, K Chakrabarty… – Proceedings of the 2009 Abstract We present a thermal-aware test-access mechanism (TAM) design and test scheduling method for system-on-chip (SOC) integrated circuits. The proposed method uses cycle-accurate power profiles for thermal simulation; it also relies on test-set partitioning, test inter