Cell level layout guidelines
• Define cell architecture—i.e., standard, full custom, datapath, etc.—and
boundary rules based on the block plan.
• Define power style and widths.
• Define special requirements—i.e., symmetry, neighbors, critical path.
• Define transistor style based on speed, power consumption, and routing
• Verify the cell DRC together with neighbors. This eliminates all possibility
of finding errors at a higher level of hierarchy.
chip floor planning tools
what is Via Programmability
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