Challenges at analog cmos for low vdd
Challenges at 0.5 V analog cmos
The most basic way to achieve amplification with a MOS
transistor is the common source configuration with an active load .
The required input (gate) bias is VT +(VGS−VT) and the optimal output
(drain) bias is VDD/2 for an output swing of VDD−2VDS,sat. At 0.5 V VDD two
limitations can occur: the output bias is typically smaller than the input bias;
and, the input swing is very limited. Clearly, it becomes very difficult to design
circuits with large input and output swings. However, as long as a sufficiently
large gain exists between input and output, this is not a strong limitation.
With a 0.5 V supply, it is very difficult to use a common drain configuration
. The output can swing sufficiently but since there is no gain between
the input and the output, the input bias and signal swing would require voltage
levels above the supply.
In a common gate configuration the input signal, output signal and 3VDS,sat
are stacked; even if we assume a large voltage gain for the stage, the available
output swing is too small for most applications. A common gate stage (or
folded cascode) can be embedded in an amplifier if followed by sufficient gain
so that no significant swings are needed at the common gate output. Similarly,
cascode topologies with all devices in saturation3 are excluded at 0.5 V since
they require a stack of the output swing and 4VDS,sat (about 0.6 V).
Of the basic transistor configurations only the common source configuration
has the potential to operate at supply voltages of 0.5 V. It is again important to
remark that this limitation stems from the required VDS,sat of about 0.15 V and
is independent of the value of VT.
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