chip IEEE PAPER 2018

ChipScale Combinatorial Atomic Navigator (C-SCAN) Low Drift Nuclear Spin Gyroscope
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14. ABSTRACT We developed a 3He-129Xe nuclear spin gyroscope probed by 87Rb atoms. We batch fabricated gyroscope cells with a yield exceeding 85% and achieved ¹²Xe T2 time of 300 sec and 3He T2 time of 3.9 hours in a 2 mm cell. We developed techniques ABSTRACT This paper presents a scalable 28-GHz phased-array architecture suitable for fifth- generation (5G) communication links based on four-channel (2 2) transmit/receive (TRX) quadcore chips in SiGe BiCMOS with flip- chip packaging. Each channel of the quad-core

Functionality and Performance of the Subretinal Implant Chip Alpha AMS
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Electronic retinal implants have been developed and are marketed as a therapeutic option for blind people suffering from degenerative retinal diseases such as retinitis pigmentosa. The functionality of subretinal implants depends heavily on the performance of the electronic

Inhibition of Chronic Osteomyelitis using Sustained Release of Drug from Biodegradable Polymeric Chip
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Despite the recent advances in medical and surgical therapies, the treatment of chronic osteomyelitis (bone and joint infection), especially the treatment of Methicillin-Resistant Staphylococcus Aureus (MRSA) osteomyelitis, still remains challenging and is associated ABSTRACT Ultrasound in the presence of gas-filled microbub-bles can be used to enhance local uptake of drugs and genes. To study the drug delivery potential and its underlying physical and biological mechanisms, an in vitro vessel model should ideally include 3-D cell

Design and characterization of the monolithic matrices of the H35DEMO chip
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The H35DEMO was the first large area demonstrator fabricated to validate High Voltage/High Resistivity Depleted Monolithic Active Pixels (HV/HR-DMAPS) as a technology feasible for ATLAS pixel detector upgrade foreseen for the High-Luminosity LHC phase

Study of Al-doped ZnO Transparent Stimulus Electrode for Fully Implantable Retinal Prosthesis with Three-dimensionally Stacked Retinal Prosthesis Chip
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To realize a three-dimensionally (3D) stacked retinal prosthesis chip having a large stimulus electrode area and a large photodiode area, the fundamental properties of an Al-doped ZnO transparent stimulus electrode were investigated in detail. The test samples were fabricated ABSTRACT In this letter, a compact 60-GHz on- chip bandpass filter (BPF) is presented using integrated passive devices (IPD) technology on a GaAs substrate. An E-shaped dual-mode resonator and stepped impedance resonator (SIR) were adopted in this design for a

On- chip intercalated-graphene inductors fornext-generation radio frequency electronics
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The Internet of Things (IoT) promises unprecedented connectivity between people and 50 billion things by 2020 1, 2, with a potential economic impact of US $2.7 trillion to US $6.2 trillion per year by 2025 1, 3. This will require a tremendous number of miniaturized wireless

Lab-on-[315_TD $ DIFF] a- Chip Platforms for Biophysical Studies of Cancer with Single-Cell Resolution
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Recent cancer research has more strongly emphasized the biophysical aspects of tumor development, progression, and microenvironment. In addition to genetic modifications and mutations in cancer cells, it is now well accepted that the physical properties of cancer cells Gain-Cell eDRAM (GC-eDRAM) is an interesting, high-density alternative to SRAM and conventional 1T-1C eDRAM for a large range of VLSI system-onchip (SoC) applications, including ultra-low power systems such as biomedical implants [17], wireless ABSTRACT Multicast communication can greatly enhance the performance of Networks-on- Chip . Currently most multicast routing algorithms are either tree-based or path-based. The former has low latency but needs to solve multicast deadlocks through additional hardware

On- chip plasmonic cavity-enhanced spontaneous emission rate at the zero-phonon line
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Highly confined surface plasmon polariton (SPP) modes can be utilized to enhance light- matter interaction at the single emitter level of quantum optical systems [1-4]. Dielectric- loaded SPP waveguides (DLSPPWs) confine SPPs laterally with relatively low propagation ABSTRACT We have demonstrated on- chip optical delay lines that consist of cascaded Bragg grating segments. Our results show that the band gap and the group index of cascaded gratings are very similar to that of a single grating segment, which means longer time delay

Fingerprint-Sclera based Multimodal Biometric Authentication System using Hybrid Genetic Intelligent Technique for System on Chip Application
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ABSTRACT Multimodal biometrics is used to solve many problems associated with unimodal biometric authentication accuracy. The problem arises due to data acquisition noise, spoofing biometric identity and non-universality of biometric features. A significant

An Experimental Investigation on Strength Properties of Steel Fiber Chip for M-25 and M-30 Grades of Concrete
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ABSTRACT : This experimental investigation is carried out to experimental study the different strength characteristics of concrete with partial replacement of steel fiber with M-25M-30 grade concrete. The main objective of this investigation work is to improve the strength

Upgrade of the YARR DAQ System for the ATLAS Phase-II Pixel Detector Readout Chip
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Page 1. PoS(TWEPP-17)076 Upgrade of the YARR DAQ System for the ATLAS Phase-II Pixel Detector Readout Chip Nikola Lazar Whallon∗† University of Washington (US) E-mail: Timon Heim LBNL (US) E-mail: Maurice Garcia-Sciveres

A CMOS 256-pixel Photovoltaics-powered Implantable Chip with Active Pixel Sensors and Iridium-oxide Electrodes for Subretinal Prostheses
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Retinitis pigmentosa (RP) and age-related macular degeneration (AMD) are two diseases in which degenerated photoreceptors fail to transfer visual information to other retinal cells in the retinal network. As a result, the patients lose their vision in the late stage. A promising

High-level Estimation and Exploration of Reliability for Multi-processor System-on- chip
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The last few decades have witnessed continuous scaling of CMOS technology, guided by Moores Law [136], to support devices with higher speed, less area, and less power. Though there have been varying arguments on how long the scaling can be continued, it is

A SDN Solution for System-on- Chip World
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ABSTRACT System on chips (SoCs) are all around us in todays world. Therefore, in this paper we propose a flexible, technologyaware SoC design, named as Cloud-of-Chips (CoC), which is able to change its characteristics, such as routing logic, transmission paths

An IV Circuit with Combined Compensation for Infrared Receiver Chip
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ABSTRACT This paper proposes a novel combined compensation structure in the infrared receiver chip . For the infrared communication chip the current-voltage (IV) convert circuit is crucial and important. The circuit is composed by the transimpedance amplifier (TIA) and the

Optimize Cram on Conventional Network-on- Chip Using ELIDER
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ABSTRACT A conservative Network-on- Chip (NoC) router uses input buffers to accumulate incoming packets. Minimally buffered, single-cycle deflection routing will overlap the operations (Injection, Ejection, Pre-emption, Re-ejection) into a single module effect in a

Noise Characteristics of a High Dynamic Range Camera with Four- Chip Optical System
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ABSTRACT : HDR (high dynamic range) imaging has recently been applied to video systems, including the next-generation UHDTV (ultrahigh definition television) format. This format requires a camera with a dynamic range of over 15 f-stops and a signal to noise SN-ratio

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ABSTRACT Microfluidic Lab-on-a- chip (LoC) systems provide a miniaturized platform for sample processing and biological/medical diagnostics. This system provides great potential in personalized and localized point-of-care diagnostic applications. However, despite the

Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator
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ABSTRACT : This article presents the analysis and comparison of two powerful tools to explore design space and study multi-core microprocessors. Heracles, developed at the MIT, is a modular tool to create MIPS multi-core processors. Its modularity allows quick development

On- chip interference studies from a propagative perspective: implications of technology choices on the EMC performance of ICs
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In the past years, integration levels in electronic systems have been continuously increasing so as to enable the development of high-performance products and applications [1, 2]. This implies that different electronic functional blocks (microcontrollers, RF modules, A/D

PeakPass: A Machine Learning Approach for ChIPSeq Blacklisting.
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ABSTRACT WIMBERLEY, CHARLES ERIC. PeakPass: A Machine Learning Approach for ChIPSeq Blacklisting.(Under the direction of Dr. Steffen Heber.) High-throughput DNA sequencing experiments, particularly ChIPSeq experiments, suffer from

A study of SEU-tolerant latches for the RD53A chip
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The 65 nm CMOS process is a promising technology for the pixel readout chips at HL-LHC (High Luminosity-LHC) in terms of high integration density and a first 65 nm demonstrator chip RD53A, containing 76800 pixels of 50 50m² was submitted end of August 2017

Hardening the Hardware: A Reverse-engineering Resilient Secure Chip
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ABSTRACT With the globalization of integrated circuit (IC) supply chain, the semi-conductor industry is facing a number of security threats, such as Intellectual Property (IP) piracy, hardware Trojans, and counterfeiting. To defend against such threats at the hardware level ABSTRACT We propose Chipto- Chip Capacitive Coupled Communication (5C) to increase off- chip communication through the metal plate on the side wall of the chip packaging, as the chip to chip spacing for the state of the art electronic designs has been reduced due to the

A Comparative Study of Chip Morphology, Surface Roughness and Tool Wear of Machining Rolled Aluminum using the Advanced Cutting Tools
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Machining of aluminum and its alloy are very difficult due to the formation of built-up edge (BUE) on the surface. This can be minimized by selection of proper cutting speed, feed and cutting tool material. Surface integrity and tool life during machining significantly affect the ABSTRACT Loihi is a 60 mm2 chip fabricated in Intels 14nm process that advances the state- of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic

Throughput Analysis of Per-Antenna Rate Control with Linear ChipLevel Equalization
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ABSTRACT In this paper the achievable performance gains of Per-Antenna Rate Control (PARC) for Code Division Multiple Access (CDMA) transmission with different linear chiplevel equalization algorithms are investigated. High Speed Downlink Packet Access

Dont Skip the Equine Chip : A review of new equine microchip regulations
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Margaux Buchanan, DVM, from South Shore Equine Clinic and Diagnostic Center in Plympton, Massachusetts, has noticed a shift in attitudes about microchips among her clients. My clients frequently ask for microchips, and they respond positively when I

SiGe: C 0.25m Digital Frequency Divider For An On- Chip Phase-Noise Measurement Circuit
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PaperIt is a student paper ABSTRACT A low phase noise and wide-bandwidth frequency divider has been developed in a 0.25m SiGe: C process. This paper discusses the BiCMOS design improvements used for ultra low phase noise applications like on- chip

The Analysis of Different Types of IoT Sensors and security trend as Quantum chip for Smart City Management
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ABSTRACT : The life on earth and the sense of the change in surroundings is highly depends on each other. So sensors have become part of our daily life. Recent years witnessed tremendous advances in wirelessly networks and its sensors. Wireless sensor nodes are

Dual Coding Technique to Reduce Dynamic Power Dissipation and Delay in Network on Chip (NOC)
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ABSTRACT In a typical bus system of NOC, 10% of the power dissipation is static or leakage and 90% is dynamic power. Hence, Dynamic power dissipation reduction is main objective of our current research work. In our current research work power dissipation is reduced in

Design and fabrication of a microfluidic chip for tumor spheroid formation and culture
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ABSTRACT Nowadays, we are witnesses of deaths caused by cancer in large statistical amounts. Vast number of investigations are conducted for anticancer drug evaluation on human and animal cells using traditional two-dimensional and three-dimensional culturing

Operational Evaluation of Network on Chip Topologies
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ABSTRACT -The Network on Chip (NoC) has developed as a substitute for wired or interconnection network for System on Chip (SoC). It acts as a way to reduce existing problems of interference, bandwidth desideratum, and potential and makes clock distribution

CAS-BUS: a Test Access Mechanism and a Toolbox Environment for Core-based System Chip Testing
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ABSTRACT As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves some of the new problems the test industry has to deal with