CMOS pipeline ADC-analog


14 bit 50 ms/s 0.18 µm CMOS pipeline ADC based on digital error calibration

FREE-DOWNLOAD [PDF] KH Lee, YJ Kim, KS Kim… – Electronics letters, 2009
Described is a 14 bit 50 MS/s CMOS four-stage pipeline A/D conver- ter (ADC)-based on a digital
code-error calibration. The proposed calibration technique measures the capacitor mismatch
errors of the front-end multiplying DAC (MDAC) with the back-end pipeline stages while 





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