cmos vco design project




Hi,
Here is few tips for your project
1. understanding the specifications
2. for vco there are few critical parameters, power dissipation,
swing of vco, phase noise, inductor, frequency range, you have to understand all the
parameters in details and relationship with circuit and mathematical ewuations
3. circuit topology
4. you can go through previous vco design projects or thesis for a outlook of your project.

hope this tips help you
Sanjeev
Re: help in cmos vco design project

You can use veriloga model of vco for the system level analysis

module vco(in,out);
input in;
output out;
voltage in,out;
// SJM added
voltage vin;

parameter real f0 = 1.0M from (0:inf), // center frequency
kf = 100K, // frequency coefficient Hz/V
lockrange = 3, // lockrange according input voltage
vin_offset = 0,// input dc offset, e.g. V(in)=vin_offs et -> f0
vout_offset = 0, // output dc offset
vout_mag = 1, // output magnitude
phi0 = 0;// dc phase, given in radian

real w;

analog
begin
vin = V(in) – vin_offset;
if (vin > lockrange) vin = lockrange;
else
if (vin < -lockrange) vin = -lockrange; w = `M_TWO_PI * (f0 + kf*vin); V(out) <+ vout_offset + vout_mag*sin(w*$realtime + phi0); end endmodule




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