A 4-channel Time Interleaved Sampler based 3-5 GHz band CMOS Radar IC in 0.13 mm for Surveillance
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CMOS UWB radar IC realized in a 0.13 um CMOS technology for surveillance. Sampling resolution and detectable range of the proposed IC are determined to be 3 cm and 15 m, respectively, to serve a surveillance function. To reduce the scan time while satisfying

A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS
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ABSTRACT A 1 GHz intermediate frequency, 16-element, 4-beam digital beamformer facilitates multi-in multi-out, 5G mobile, and other emerging communication standards. Digital beamforming has been limited by high power consumption, large die area, and the ABSTRACT High speed optical interconnects require low-power compact electro-optical transmit modules comprising driver circuits and optical modulators. This paper presents a low power 56 Gb/s non-return-to-zero CMOS inverter based driver in 28 nm fully depleted

Multi-MGy total ionizing dose induced MOSFET variability effects on radiation hardened CMOS image sensor performances
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I. INTRODUCTION MOS Image Sensors (CIS) are today the main solid-state image sensor technology and they are widely used for the development of various scientific applications, thanks to their high performances, high integration capabilities and low power consumption. Their demand

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ABSTRACT -This paper presents a 4-stage pipelined analog to digital converter architecture with a 4-bit resolution per each stage, enabled with the help of a successive approximation register based sub-ADC. Successive approximation register (SAR) ADC architectures are

Sensitivity Enhancement of a Vertical-Type CMOS Hall Device for a Magnetic Sensor
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ABSTRACT This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current

A 2 Gsps waveform digitizer ASIC in CMOS 180 nm technology
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ABSTRACT : The design and measurement results of a waveform digitizer based on the Switched Capacitor Array (SCA) architecture, fabricated in CMOS 180 nm technology, are presented. The prototype ASIC containing two channels inside is fully functional at a CMOS integrated circuit design for wireless power transfer intends to report the state-of-the- art analog and power management IC design techniques for various wireless power transfer (WPT) systems. To propose elaborate power management solutions, the circuit designers

Analysis of Reliability for Fault Tolerant Design in NANO CMOS Logic Circuit
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ABSTRACT The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit. In this nano CMOS circuit ABSTRACT This paper presents a continuous-time multi-stage noise-shaping (MASH) delta sigma modulator (CT- M) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed

An Insight into Beyond CMOS Next Generation Computing using Quantum-dot Cellular Automata Nanotechnology
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ABSTRACT CMOS is a technology that has revolutionized the field of electronics. Over the time the processing technologies and design methodologies of CMOS devices have proved to be in full swing with the Moores law and the miniaturization paradigm. However, after surviving

A CMOS 256-pixel Photovoltaics-powered Implantable Chip with Active Pixel Sensors and Iridium-oxide Electrodes for Subretinal Prostheses
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Retinitis pigmentosa (RP) and age-related macular degeneration (AMD) are two diseases in which degenerated photoreceptors fail to transfer visual information to other retinal cells in the retinal network. As a result, the patients lose their vision in the late stage. A promising The future is the Internet of Things (IoT) and it is already here, eg, in the environmental monitoring, in the manufacturing, and in the building and home automation. By the technology of IoT, there have been millions of mobile devices that are collecting data and Emerging memories have been developed to achieve energy efficiency target in the Internet of Things era. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile (NV) memory has demonstrated attractive performance because of zero standby power

Low-power CMOS Front-end ROIC using Inverter-feedback RGC TIA for 3-D Flash LADAR Sensor
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ABSTRACT This work proposes a pixel architecture for a front-end readout integrated circuit (ROIC) using an inverter-feedback regulated-cascode (RGC) transimpedance amplifier (TIA) for the focal plane array of a three-dimensional flash laser detection and ranging sensor

Performance Evaluation of CMOS Detector using GigE vision Framework
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ABSTRACT -As the detector is key element in image generation, in the last few years, innovative solutions for the realization of these large area detectors are required especially for advanced biomedical systems with integrated detector electronics. Detector should be able Almost on a daily basis, nanoeletronic metal-oxide-semiconductor ( CMOS ) technology and device design are introduced and explored in rapidly developing semiconductor industry. This book3D TCAD Simulation for CMOS Nanoeletronic Devicespresents a self-contained

A Broadband Low Power CMOS LNA for 3.1 10.6 GHz UWB Receivers
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ABSTRACT : A new approach for designing an ultra wideband (UWB) CMOS low noise amplifier (LNA) is presented. The aim of this design is to achieve a low noise figure, reasonable power gain and low power consumption in 3.1-10.6 GHz. Also, the figure of merit (FOM) is

Design and Assessment of Type-II PLL implementing Various CMOS PFDs
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ABSTRACT This paper reflects the design and comparison of different Phase Frequency Detectors (PFD) used in Phase Locked Loop (PLL) using different logic gates. A PFD plays a major role in PLL, it detects both phase and frequency of a signal. In this paper a PFD is

Performance Evaluation of Power Reduction in CMOS Domino Logic
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S Kumar 2018 In the proposed implementation of the buffer, the transistor M6 is connected between dynamic node-Z and transistor M5, the drain of transistor M6 is connected to dynamic node- Z and source of transistor is connected to Gate of transistor M5 and input of transistor M6 is We are at the dawn of a new era. New emerging applications will revolutionize the way we communicate, share ideas, work, travel, play, watch sports, and enjoy movies; in a single word, the way we live. For Internet of Things (IoT) applications, it is estimated that up to

Characterization of the CMOS FinFET structure on single-event effects basic charge collection mechanisms and soft error modes
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Since the prediction of space-system upsets from ionizing particles by Wallmark and Marcus [Wall-62] and the first report of experimentally observed upsets in communication satellites by Binder et al. in 1975 [Bind-75], single-event effects (SEE) have been an increasing

Fabrication, CMOS integration and applications of non-volatile 3D metal oxide crossbars
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ABSTRACT As the rapid progress of memristor technology continues, multi-layer stacking of these crossbars is needed in order to maximize the use of vertical space and achieve the required density. This work is focused on designing and building three-dimensional

Annual Report to Catalyst Foundation Project title: CMOSassisted nano-bio array for neurotechnology
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No existing electrophysiology tool has been capable of both intracellular and network-level parallel recording. The patch clamp technique can perform intracellular recording but it is not suited for parallel recording due to the lack of scalability. The microelectrode array boasts

photon counting using CMOS SPAD arrays
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We present a digital architecture for fast acquisition of time correlated single photon counting (TCSPC) events from a 32 32 CMOS SPAD array (Megaframe) to the computer memory. Custom firmware was written to transmit event codes from 1024 TCSPC-enabled pixels for

Design of A 60 GHz Power Amplifier utilizing 90nm CMOS Technology
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ABSTRACT In order to satisfy the short-distance high-speed wireless transmission communication system, such as Wireless Personal Area Net-work (WPAN) applications. A 60GHz high efficiency single ended power amplifier is proposed, which is with three stages ABSTRACT This paper presents a bidirectional variable gain amplifier (BVGA) with a low imbalance between amplification directions in 65-nm CMOS process. The BVGA is composed of two symmetric bidirectional amplifiers (BA) and a distributed attenuator (DA) for ABSTRACT In this work, we discuss three novel Ti (germano-) silicidation techniques featuring respectively the pre-contact amorphization implantation (PCAI), the TiSi co-deposition, and Ti atomic layer deposition (ALD). All three techniques form TiSix (Gey) contacts with ultralow

CMOS MMIC Ready for Road A Technology Overview
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Over the years, complementary metal-oxide semiconductor ( CMOS ) technology has been popular for wireless transceiver chips with integrated radios, as evidenced by multiple chipsets in volume production. These integrated circuits (ICs) enable a variety of

Two calibration methods to improve the linearity of a CMOS image sensor
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ABSTRACT This paper presents two on-chip calibration methods for improving the linearity of a CMOS image sensor (CIS). A prototype 128 128 pixel sensor with a size of 10 um 12 um is fabricated using a 0.18 um 1P4M CIS process. Both calibration methods show obvious

Design of Voltage Controlled Oscillator in 180 nm CMOS Technology
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ABSTRACT -Voltage Controlled Oscillator is the heart of the many modern electronics as well as communication system. Hence there is necessity of VCO to operate in the GHz frequency range. This project describes a design and implementation of Five Stage Current Starved ABSTRACT In this paper, a high-efficiency frequency-reconfigurable CMOS power amplifier (PA) design technique is presented at 24 and 28 GHz using integrated tunable neutralization and matching networks. To cope with the adverse effects of gate drain

Bandwidth and Gain Enhanced PNP Phototransistor in 180nm CMOS Process
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ABSTRACT : Highly photosensitive pnp phototransistors are successfully demonstrated in a 180nm Complementary Metal Oxide Semiconductor ( CMOS ) process. Here we describe improved pnp phototransistors implemented in sizes 50 x 50 m2 and 100 x 100 m2. The ABSTRACT This paper extends N-path filtering to the code domain by proposing code- modulated local oscillator signals. A correlator-based perspective of N-path mixer receiver (RX) is presented to demonstrate interferer-rejection and desired signal reception in a code ABSTRACT The downsizing of electron devices has always been the key to promote the computer performance and energy consumption for the past 70 years since its beginning. However, it should be noted now that the downsizing of the electron devices,--such as ABSTRACT This paper presents a compact-area, low-power, highly digital analog-to-digital converter (ADC) for audio applications. The proposed converter is implemented using only oscillators and digital circuitry, without operational amplifiers nor other highly linear circuits ABSTRACT In this paper, we present a short overview of the CMOScompatible contact technology developed in our group on n-InP and p-InGaAs for Si photonic applications. Obtained results cover a wide spectrum: from surface preparation and solid-state reaction to

Performance Enhancement Of Complex Digital Circuit usingDynamic CMOS Logic
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ABSTRACT The performance of any logic circuit is measured in terms of area, delay and the power consumption of the circuit. The Power Delay Product is used as a unit to define the performance of the circuit. Static logic proves to be beneficial for simple and low fan in

Design and Performance analysis of CMOS based D Flip-Flop using Low power Techniques
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ABSTRACT In todays world, the VLSI designer totally dependent on Flip-flops as it has wide range of applications in various field of electronics. Flip-flops are widely used in spacecraft for numerous processes; these are also used in telecommunication sector for exchange the