Concepts of Timing and Delays in Verilog

The concepts of timing and delays within circuit simulations are very important because they allow a
degree of realism to be incorporated into the modelling process. In Verilog, without explicit specification
of such constraints, the outputs of pre-defined primitives and user-defined modules are all assumed to
resolve instantaneously (or at least, within one simulator timestep). This, clearly, is not enough for a
designer to work with, especially since the time taken for changes to propagate through a module may
lead to race conditions in other modules. Some designs, such as high speed microprocessors, may have
very tight timing requirements that must be met. Failure to meet these constraints may result in the
design failing to work at all, or possibly even producing invalid outputs. Thus, while the obvious aim of
the designer may be to produce a circuit that functions correctly, it is equally important that the circuit
also conforms to any timing constraints required of it.